On Mon, Mar 17, 2025 at 4:53 PM Marek Olšák <maraeo@xxxxxxxxx> wrote:
>
> I would prefer a bitmask of supported UQ IPs in device info, but this is fine too.
I can do that instead.
Alex
>
> Reviewed-by: Marek Olšák <marek.olsak@xxxxxxx>
>
> Marek
>
> On Mon, Mar 17, 2025 at 3:23 PM Alex Deucher <alexander.deucher@xxxxxxx> wrote:
>>
>> Add an INFO query to check if user queues are supported.
>>
>> Cc: marek.olsak@xxxxxxx
>> Cc: prike.liang@xxxxxxx
>> Cc: sunil.khatri@xxxxxxx
>> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 17 +++++++++++++++++
>> include/uapi/drm/amdgpu_drm.h | 8 ++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> index 3b7dfd56ccd0e..38b8983f59d3c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> @@ -1340,6 +1340,23 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
>> return -EINVAL;
>> }
>> }
>> + case AMDGPU_INFO_UQ_SUPPORTED: {
>> + struct drm_amdgpu_info_uq_supported uq_supported = {};
>> + u32 ip_type = info->query_hw_ip.type;
>> +
>> + switch (ip_type) {
>> + case AMDGPU_HW_IP_GFX:
>> + case AMDGPU_HW_IP_COMPUTE:
>> + case AMDGPU_HW_IP_DMA:
>> + if (adev->userq_funcs[ip_type])
>> + uq_supported.supported = 1;
>> + ret = copy_to_user(out, &uq_supported,
>> + min((size_t)size, sizeof(uq_supported))) ? -EFAULT : 0;
>> + return 0;
>> + default:
>> + return -EINVAL;
>> + }
>> + }
>> default:
>> DRM_DEBUG_KMS("Invalid request %d\n", info->query);
>> return -EINVAL;
>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
>> index 5dbd9037afe75..b4b6fe006af8e 100644
>> --- a/include/uapi/drm/amdgpu_drm.h
>> +++ b/include/uapi/drm/amdgpu_drm.h
>> @@ -1195,6 +1195,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
>> #define AMDGPU_INFO_GPUVM_FAULT 0x23
>> /* query FW object size and alignment */
>> #define AMDGPU_INFO_UQ_FW_AREAS 0x24
>> +/* query if user queues are supported */
>> +#define AMDGPU_INFO_UQ_SUPPORTED 0x25
>>
>> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
>> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
>> @@ -1572,6 +1574,12 @@ struct drm_amdgpu_info_uq_metadata {
>> };
>> };
>>
>> +struct drm_amdgpu_info_uq_supported {
>> + /** returns 1 if supported, 0 if not supported */
>> + __u32 supported;
>> + __u32 pad;
>> +};
>> +
>> /*
>> * Supported GPU families
>> */
>> --
>> 2.48.1
>>
