[no subject]

Also KFD_GC_VERSION(pm->dqm->dev) > IP_VERSION(10, 0, 0) is incorrect and should be >= because want to also exclude anything with a major version of 10.

Jon

> +
> +             /* For all other gfx9 ASICs,
> +              * Reduce CP_IQ_WAIT_TIME2.QUE_SLEEP to 0x1 from default
> 0x40.
>                * On a 1GHz machine this is roughly 1 microsecond, which is
>                * about how long it takes to load data out of memory during
>                * queue connect
>                * QUE_SLEEP: Wait Count for Dequeue Retry.
> +              *
> +              * Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU
>                */
> -             if (KFD_GC_VERSION(pm->dqm->dev) >= IP_VERSION(9, 4, 1) &&
> -                 KFD_GC_VERSION(pm->dqm->dev) < IP_VERSION(10, 0, 0)) {
> -                     que_sleep = 1;
> -
> -                     /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU
> */
> -                     if (amdgpu_emu_mode == 0 && pm->dqm->dev->adev-
> >gmc.is_app_apu &&
> -                     (KFD_GC_VERSION(pm->dqm->dev) == IP_VERSION(9, 4,
> 3)))
> -                             sch_wave = 1;
> -             } else {
> -                     return 0;
> -             }
> +             if (amdgpu_emu_mode == 0 && pm->dqm->dev->adev-
> >gmc.is_app_apu &&
> +                 (KFD_GC_VERSION(pm->dqm->dev) == IP_VERSION(9, 4, 3)))
> +                     sch_wave = 1;
> +
>               pm_build_dequeue_wait_counts_packet_info(pm, sch_wave,
> que_sleep,
>                       &reg_offset, &reg_data);
>
> @@ -377,7 +385,7 @@ static int pm_config_dequeue_wait_counts_v9(struct
> packet_manager *pm,
>
>       packet->data = reg_data;
>
> -     return 0;
> +     return sizeof(struct pm4_mec_write_data_mmio);
>  }
>
>  static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,
> --
> 2.34.1