Applied. Thanks!
On Wed, Mar 12, 2025 at 11:28 PM Wang, Yang(Kevin)
<KevinYang.Wang@xxxxxxx> wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> It looks good to me.
>
> Reviewed-by: Yang Wang <kevinyang.wang@xxxxxxx>
>
> Best Regards,
> Kevin
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Tomasz Pakula
> Sent: Wednesday, March 12, 2025 05:39
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
> Subject: [PATCH] drm/amdgpu/pm: Handle SCLK offset correctly in overdrive for smu 14.0.2
>
> Currently, it seems like the code was carried over from RDNA3 because it assumes two possible values to set. RDNA4, instead of having:
> 0: min SCLK
> 1: max SCLK
> only has
> 0: SCLK offset
>
> This change makes it so it only reports current offset value instead of showing possible min/max values and their indices. Moreover, it now only accepts the offset as a value, without the indice index.
>
> Additionally, the lower bound was printed as %u by mistake.
>
> Old:
> OD_SCLK_OFFSET:
> 0: -500Mhz
> 1: 1000Mhz
> OD_MCLK:
> 0: 97Mhz
> 1: 1259MHz
> OD_VDDGFX_OFFSET:
> 0mV
> OD_RANGE:
> SCLK_OFFSET: -500Mhz 1000Mhz
> MCLK: 97Mhz 1500Mhz
> VDDGFX_OFFSET: -200mv 0mv
>
> New:
> OD_SCLK_OFFSET:
> 0Mhz
> OD_MCLK:
> 0: 97Mhz
> 1: 1259MHz
> OD_VDDGFX_OFFSET:
> 0mV
> OD_RANGE:
> SCLK_OFFSET: -500Mhz 1000Mhz
> MCLK: 97Mhz 1500Mhz
> VDDGFX_OFFSET: -200mv 0mv
>
> Setting this offset:
> Old: "s 1 <offset>"
> New: "s <offset>"
>
> Signed-off-by: Tomasz Pakuła <tomasz.pakula.oficjalny@xxxxxxxxx>
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 59 ++++++-------------
> 1 file changed, 18 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> index 5cad09c5f2ff..62bd9647541a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> @@ -1193,16 +1193,9 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu,
> PP_OD_FEATURE_GFXCLK_BIT))
> break;
>
> - PPTable_t *pptable = smu->smu_table.driver_pptable;
> - const OverDriveLimits_t * const overdrive_upperlimits =
> - &pptable->SkuTable.OverDriveLimitsBasicMax;
> - const OverDriveLimits_t * const overdrive_lowerlimits =
> - &pptable->SkuTable.OverDriveLimitsBasicMin;
> -
> size += sysfs_emit_at(buf, size, "OD_SCLK_OFFSET:\n");
> - size += sysfs_emit_at(buf, size, "0: %dMhz\n1: %uMhz\n",
> - overdrive_lowerlimits->GfxclkFoffset,
> - overdrive_upperlimits->GfxclkFoffset);
> + size += sysfs_emit_at(buf, size, "%dMhz\n",
> + od_table->OverDriveTable.GfxclkFoffset);
> break;
>
> case SMU_OD_MCLK:
> @@ -1336,13 +1329,9 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu,
> size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
>
> if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
> - smu_v14_0_2_get_od_setting_limits(smu,
> - PP_OD_FEATURE_GFXCLK_FMIN,
> - &min_value,
> - NULL);
> smu_v14_0_2_get_od_setting_limits(smu,
> PP_OD_FEATURE_GFXCLK_FMAX,
> - NULL,
> + &min_value,
> &max_value);
> size += sysfs_emit_at(buf, size, "SCLK_OFFSET: %7dMhz %10uMhz\n",
> min_value, max_value);
> @@ -2417,36 +2406,24 @@ static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu,
> return -ENOTSUPP;
> }
>
> - for (i = 0; i < size; i += 2) {
> - if (i + 2 > size) {
> - dev_info(adev->dev, "invalid number of input parameters %d\n", size);
> - return -EINVAL;
> - }
> -
> - switch (input[i]) {
> - case 1:
> - smu_v14_0_2_get_od_setting_limits(smu,
> - PP_OD_FEATURE_GFXCLK_FMAX,
> - &minimum,
> - &maximum);
> - if (input[i + 1] < minimum ||
> - input[i + 1] > maximum) {
> - dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
> - input[i + 1], minimum, maximum);
> - return -EINVAL;
> - }
> -
> - od_table->OverDriveTable.GfxclkFoffset = input[i + 1];
> - od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
> - break;
> + if (size != 1) {
> + dev_info(adev->dev, "invalid number of input parameters %d\n", size);
> + return -EINVAL;
> + }
>
> - default:
> - dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
> - dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
> - return -EINVAL;
> - }
> + smu_v14_0_2_get_od_setting_limits(smu,
> + PP_OD_FEATURE_GFXCLK_FMAX,
> + &minimum,
> + &maximum);
> + if (input[0] < minimum ||
> + input[0] > maximum) {
> + dev_info(adev->dev, "GfxclkFoffset must be within [%d, %u]!\n",
> + minimum, maximum);
> + return -EINVAL;
> }
>
> + od_table->OverDriveTable.GfxclkFoffset = input[0];
> + od_table->OverDriveTable.FeatureCtrlMask |= 1U <<
> +PP_OD_FEATURE_GFXCLK_BIT;
> break;
>
> case PP_OD_EDIT_MCLK_VDDC_TABLE:
> --
> 2.48.1
>
