Make all resources available to user queues.
Suggested-by: Sunil Khatri <sunil.khatri@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index afc2ce344df52..71dce64a0ea32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -157,14 +157,14 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
* Set GFX pipe 0 queue 1-7 for MES scheduling
* mask = 1111 1110b
*/
- adev->mes.gfx_hqd_mask[i] = 0xFE;
+ adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE;
else
/*
* GFX pipe 0 queue 0 is being used by Kernel queue.
* Set GFX pipe 0 queue 1 for MES scheduling
* mask = 10b
*/
- adev->mes.gfx_hqd_mask[i] = 0x2;
+ adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2;
}
}
@@ -172,7 +172,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
/* use only 1st MEC pipes */
if (i >= adev->gfx.mec.num_pipe_per_mec)
continue;
- adev->mes.compute_hqd_mask[i] = 0xc;
+ adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC;
}
for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
--
2.48.1
