ping on this series.
Alex
On Wed, Feb 26, 2025 at 11:09 PM Alex Deucher <alexander.deucher@xxxxxxx> wrote:
>
> Just use the default values. There's not need to
> get the value from hardware and it could cause problems
> if we do that at runtime and gfxoff is active.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 48 ++++++++++++++++++--------
> 1 file changed, 33 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 667c8013b7738..804e9552a608a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -52,6 +52,24 @@
>
> #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
>
> +#define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
> +#define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
> +#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
> +#define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
> +#define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
> +#define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
> +#define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
> +
> +#define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
> +#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
> +#define regCP_MQD_CONTROL_DEFAULT 0x00000100
> +#define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
> +#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
> +#define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
> +#define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
> +#define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
> +
> +
> MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
> MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
> MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
> @@ -2926,25 +2944,25 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
>
> /* set up mqd control */
> - tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
> + tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
> tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
> tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
> mqd->cp_gfx_mqd_control = tmp;
>
> /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
> - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
> + tmp = regCP_GFX_HQD_VMID_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
> mqd->cp_gfx_hqd_vmid = 0;
>
> /* set up default queue priority level
> * 0x0 = low priority, 0x1 = high priority */
> - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
> + tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
> mqd->cp_gfx_hqd_queue_priority = tmp;
>
> /* set up time quantum */
> - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
> + tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
> mqd->cp_gfx_hqd_quantum = tmp;
>
> @@ -2966,7 +2984,7 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
>
> /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
> rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
> - tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
> + tmp = regCP_GFX_HQD_CNTL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
> tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
> #ifdef __BIG_ENDIAN
> @@ -2975,7 +2993,7 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_gfx_hqd_cntl = tmp;
>
> /* set up cp_doorbell_control */
> - tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
> + tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
> if (prop->use_doorbell) {
> tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
> DOORBELL_OFFSET, prop->doorbell_index);
> @@ -2987,7 +3005,7 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_rb_doorbell_control = tmp;
>
> /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
> - mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
> + mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
>
> /* active the queue */
> mqd->cp_gfx_hqd_active = 1;
> @@ -3090,14 +3108,14 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
>
> /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
> - tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
> + tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
> (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
>
> mqd->cp_hqd_eop_control = tmp;
>
> /* enable doorbell? */
> - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
> + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
>
> if (prop->use_doorbell) {
> tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> @@ -3126,7 +3144,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
>
> /* set MQD vmid to 0 */
> - tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
> + tmp = regCP_MQD_CONTROL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
> mqd->cp_mqd_control = tmp;
>
> @@ -3136,7 +3154,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
>
> /* set up the HQD, this is similar to CP_RB0_CNTL */
> - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
> + tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
> (order_base_2(prop->queue_size / 4) - 1));
> tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
> @@ -3161,7 +3179,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
> tmp = 0;
> /* enable the doorbell if requested */
> if (prop->use_doorbell) {
> - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
> + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> DOORBELL_OFFSET, prop->doorbell_index);
>
> @@ -3176,17 +3194,17 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
> mqd->cp_hqd_pq_doorbell_control = tmp;
>
> /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
> - mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
> + mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
>
> /* set the vmid for the queue */
> mqd->cp_hqd_vmid = 0;
>
> - tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
> + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
> mqd->cp_hqd_persistent_state = tmp;
>
> /* set MIN_IB_AVAIL_SIZE */
> - tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
> + tmp = regCP_HQD_IB_CONTROL_DEFAULT;
> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
> mqd->cp_hqd_ib_control = tmp;
>
> --
> 2.48.1
>
