For cores 1 through 7 repair the core reset sequence by adjusting offsets to access the expected registers. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index b8f06e9c9e62..1a28bc35385a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -1104,24 +1104,20 @@ static void jpeg_v4_0_3_core_stall_reset(struct amdgpu_ring *ring) WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_UVD_JMI_CLIENT_STALL, reg_offset, 0x1F); - SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, - regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, - 0x1F, 0x1F); + SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, + reg_offset, 0x1F, 0x1F); WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_JPEG_LMI_DROP, reg_offset, 0x1F); - WREG32_SOC15_OFFSET(JPEG, jpeg_inst, - regJPEG_CORE_RST_CTRL, - reg_offset, 1 << ring->pipe); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_UVD_JMI_CLIENT_STALL, reg_offset, 0x00); WREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JMI0_JPEG_LMI_DROP, reg_offset, 0x00); - WREG32_SOC15_OFFSET(JPEG, jpeg_inst, - regJPEG_CORE_RST_CTRL, - reg_offset, 0x00); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); } static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) -- 2.25.1
