[AMD Official Use Only - AMD Internal Distribution Only]
-----Original Message-----
From: Kenneth Feng <kenneth.feng@xxxxxxx>
Sent: Friday, February 14, 2025 19:15
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wang, Yang(Kevin) <KevinYang.Wang@xxxxxxx>; Feng, Kenneth <Kenneth.Feng@xxxxxxx>
Subject: [PATCH] drm/amd/pm: extend the gfxoff delay for compute workload
extend the gfxoff delay for compute workload on smu 14.0.2/3 to fix the kfd test issue.
Signed-off-by: Kenneth Feng <kenneth.feng@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 +++
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 14 ++++++++++++++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 +++++++++++++++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 ++
5 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index b9bd6654f317..4ae6fde6c69c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -776,6 +776,9 @@ static void amdgpu_gfx_do_off_ctrl(struct amdgpu_device *adev, bool enable, {
unsigned long delay = GFX_OFF_DELAY_ENABLE;
+ if (amdgpu_dpm_need_extra_gfxoff_delay(adev))
+ delay *= 5;
+
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return;
[kevin]:
It's better to adjust the code position to avoid unnecessary condition check.
After that,
Reviewed-by: Yang Wang <kevinyang.wang@xxxxxxx>
Best Regards,
Kevin
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 7a22aef6e59c..87de50b73a0e 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -873,6 +873,20 @@ int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
return ret;
}
+bool amdgpu_dpm_need_extra_gfxoff_delay(struct amdgpu_device *adev) {
+ struct smu_context *smu = adev->powerplay.pp_handle;
+ bool ret = false;
+
+ if (is_support_sw_smu(adev)) {
+ mutex_lock(&adev->pm.mutex);
+ ret = smu_need_extra_gfxoff_delay(smu);
+ mutex_unlock(&adev->pm.mutex);
+ }
+
+ return ret;
+}
+
uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) {
struct smu_context *smu = adev->powerplay.pp_handle; diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index 1f5ac7e0230d..312ad348ce82 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -470,6 +470,7 @@ int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value); int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value); int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value); int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
+bool amdgpu_dpm_need_extra_gfxoff_delay(struct amdgpu_device *adev);
uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
enum gfx_change_state state);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index a1164912f674..61cd170ec30a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -133,6 +133,21 @@ int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
return 0;
}
+bool smu_need_extra_gfxoff_delay(struct smu_context *smu) {
+ bool ret = false;
+
+ if (!smu->pm_enabled)
+ return false;
+
+ if (((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2)) ||
+ (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 3))) &&
+ smu->workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE))
+ return true;
+
+ return ret;
+}
+
int smu_set_soft_freq_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 3630593bce61..82f06c2a752d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1626,6 +1626,8 @@ int smu_set_residency_gfxoff(struct smu_context *smu, bool value);
int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
+bool smu_need_extra_gfxoff_delay(struct smu_context *smu);
+
int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
--
2.34.1
