[Public]
The implementation of the gfx11/gfx12 pipe reset is derived from the gfx9 pipe reset sequence. Consequently, the driver sequence may not undergo significant changes except for incorporating gfx11/gfx12 firmware support for the pipe reset. To reduce the effort needed to address merge conflicts, could these series implementations be advanced to upstream?
Regards,
Prike
> -----Original Message-----
> From: Liang, Prike <Prike.Liang@xxxxxxx>
> Sent: Sunday, January 26, 2025 4:38 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian
> <Christian.Koenig@xxxxxxx>; Lazar, Lijo <Lijo.Lazar@xxxxxxx>; Liang, Prike
> <Prike.Liang@xxxxxxx>
> Subject: [PATCH 4/4] drm/amdgpu/gfx12: Implement the GFX12 KCQ pipe reset
>
> Implement the GFX12 KCQ pipe reset, disable the GFX12 kernel compute queue
> until the CPFW fully supports it.
>
> Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 89 +++++++++++++++++++++++++-
> 1 file changed, 87 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 14ea7c1e827e..c5d07d5aa495 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -53,6 +53,7 @@
>
> #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
> static uint32_t me_fw_start_pc;
> +static uint32_t mec_fw_start_pc;
>
> MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
> MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
> @@ -2127,6 +2128,7 @@ static void gfx_v12_0_config_gfx_rs64(struct
> amdgpu_device *adev)
> tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL,
> MEC_PIPE2_RESET, 0);
> tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL,
> MEC_PIPE3_RESET, 0);
> WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
> + mec_fw_start_pc = RREG32(SOC15_REG_OFFSET(GC, 0,
> +regCP_MEC_RS64_INSTR_PNTR));
> }
>
> static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)
> @@ -5356,6 +5358,87 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring
> *ring, unsigned int vmid)
> return amdgpu_ring_test_ring(ring);
> }
>
> +static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) {
> +
> + struct amdgpu_device *adev = ring->adev;
> + uint32_t reset_pipe = 0, clean_pipe = 0;
> + int r;
> +
> + if (!gfx_v12_pipe_reset_support(adev))
> + return -EOPNOTSUPP;
> +
> + gfx_v12_0_set_safe_mode(adev, 0);
> + mutex_lock(&adev->srbm_mutex);
> + soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> +
> + reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
> + clean_pipe = reset_pipe;
> +
> + if (adev->gfx.rs64_enable) {
> +
> + switch (ring->pipe) {
> + case 0:
> + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE0_RESET, 1);
> + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE0_RESET, 0);
> + break;
> + case 1:
> + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE1_RESET, 1);
> + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE1_RESET, 0);
> + break;
> + case 2:
> + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE2_RESET, 1);
> + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE2_RESET, 0);
> + break;
> + case 3:
> + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE3_RESET, 1);
> + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_RS64_CNTL,
> + MEC_PIPE3_RESET, 0);
> + break;
> + default:
> + break;
> + }
> + WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
> + WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
> + r = RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) -
> mec_fw_start_pc;
> + } else {
> + switch (ring->pipe) {
> + case 0:
> + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
> + MEC_ME1_PIPE0_RESET,
> 1);
> + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> + MEC_ME1_PIPE0_RESET,
> 0);
> + break;
> + case 1:
> + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
> + MEC_ME1_PIPE1_RESET,
> 1);
> + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> + MEC_ME1_PIPE1_RESET,
> 0);
> + break;
> + default:
> + break;
> + }
> + WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
> + WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
> + }
> +
> + soc24_grbm_select(adev, 0, 0, 0, 0);
> + mutex_unlock(&adev->srbm_mutex);
> + gfx_v12_0_unset_safe_mode(adev, 0);
> +
> + dev_info(adev->dev,"The ring %s pipe resets: %s\n", ring->name,
> + r == 0 ? "successfully" : "failed");
> + /* Need the ring test to verify the pipe reset result.*/
> + return 0;
> +
> +}
> static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) {
> struct amdgpu_device *adev = ring->adev; @@ -5366,8 +5449,10 @@
> static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
>
> r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
> if (r) {
> - dev_err(adev->dev, "reset via MMIO failed %d\n", r);
> - return r;
> + dev_warn(adev->dev,"fail(%d) to reset kcq and try pipe reset\n", r);
> + r = gfx_v12_0_reset_compute_pipe(ring);
> + if (r)
> + return r;
> }
>
> r = amdgpu_bo_reserve(ring->mqd_obj, false);
> --
> 2.34.1
