[AMD Official Use Only - AMD Internal Distribution Only]
typo:
amdgpu_device_wb_put() -> amdgpu_device_wb_free()
Best Regards,
Kevin
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Wang, Yang(Kevin)
Sent: Friday, February 7, 2025 17:26
To: SHANMUGAM, SRINIVASAN <SRINIVASAN.SHANMUGAM@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; SHANMUGAM, SRINIVASAN <SRINIVASAN.SHANMUGAM@xxxxxxx>; cao, lin <lin.cao@xxxxxxx>; Chen, JingWen (Wayne) <JingWen.Chen2@xxxxxxx>; Liu, Shaoyun <Shaoyun.Liu@xxxxxxx>
Subject: RE: [PATCH] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11
[AMD Official Use Only - AMD Internal Distribution Only]
[AMD Official Use Only - AMD Internal Distribution Only]
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Srinivasan Shanmugam
Sent: Friday, February 7, 2025 17:16
To: Koenig, Christian <Christian.Koenig@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; SHANMUGAM, SRINIVASAN <SRINIVASAN.SHANMUGAM@xxxxxxx>; cao, lin <lin.cao@xxxxxxx>; Chen, JingWen (Wayne) <JingWen.Chen2@xxxxxxx>; Liu, Shaoyun <Shaoyun.Liu@xxxxxxx>
Subject: [PATCH] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11
This commit introduces enhancements to the handling of the cleaner shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are handled in a controlled manner and avoiding the
race conditions.
- The CP (Compute Processor) firmware has been updated to use a private
bus for accessing specific registers, avoiding unnecessary operations
that could lead to issues in VF (Virtual Function) mode.
- The cleaner shader fence memory address is now set correctly in the
`mes_set_hw_res_pkt` structure, allowing for proper synchronization of
the cleaner shader execution. This is done by calculating the address
using the write-back memory base address and the cleaner fence offset.
- **Memory Offset Retrieval**: The line `ret =
amdgpu_device_wb_get(adev, &cleaner_fence_offset);` retrieves the
offset for the cleaner shader fence from the write-back (WB) memory.
This is important for ensuring that the cleaner shader can synchronize
its execution properly, as the offset is necessary to calculate the
exact memory address where the fence will be located.
- **Setting Cleaner Shader Fence Address**: The line
`mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = adev->wb.gpu_addr +
(cleaner_fence_offset * 4);` sets the memory address for the cleaner
shader fence in the `mes_set_hw_res_pkt` structure. This address is
calculated by adding the base GPU address of the write-back memory to
the calculated offset. By setting this address, the MES (Microcode
Execution Scheduler) knows where to check for synchronization related
to the cleaner shader, ensuring that it operates correctly and that
the GPU is in a stable state before executing new tasks.
Cc: lin cao <lin.cao@xxxxxxx>
Cc: Jingwen Chen <Jingwen.Chen2@xxxxxxx>
Cc: Christian König <christian.koenig@xxxxxxx>
Cc: Alex Deucher <alexander.deucher@xxxxxxx>
Suggested-by: Shaoyun Liu <shaoyun.liu@xxxxxxx>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index bf51f3dcc130..d8e992c4adeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -745,14 +745,20 @@ static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) {
int size = 128 * PAGE_SIZE;
int ret = 0;
+ u32 cleaner_fence_offset;
struct amdgpu_device *adev = mes->adev;
union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
+ ret = amdgpu_device_wb_get(adev, &cleaner_fence_offset);
+ if (ret)
+ return ret;
mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
+ mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = adev->wb.gpu_addr +
+ (cleaner_fence_offset * 4);
[kevin]:
The mes_v11_0_set_hw_resources_1() function will be called during driver suspend/resume stage: mes_v11_0_resume() -> mes_v11_0_hw_init() -> mes_v11_0_set_hw_resources_1().
In above case, the code seems introduce a new memory leak issue when call function amdgpu_device_wb_get(), and no place to call function amdgpu_device_wb_put() to release it.
Please double check.
Best Regards,
Kevin
ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
--
2.34.1
