On Tue, Feb 4, 2025 at 9:48 AM Christian König
<ckoenig.leichtzumerken@xxxxxxxxx> wrote:
>
> Apply the same changes to gfx8 as done to gfx9.
>
> Untested and probably needs some more work.
>
> Signed-off-by: Christian König <christian.koenig@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 86 ++++++++++++---------------
> 1 file changed, 38 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 6a025438f9d0..f57301ebbd9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6201,12 +6201,45 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
>
> }
>
> +static void gfx_v8_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
> + int mem_space, int opt, uint32_t addr0,
> + uint32_t addr1, uint32_t ref, uint32_t mask,
> + uint32_t inv)
> +{
> + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
> + amdgpu_ring_write(ring,
> + /* memory (1) or register (0) */
> + (WAIT_REG_MEM_MEM_SPACE(mem_space) |
> + WAIT_REG_MEM_OPERATION(opt) | /* wait */
> + WAIT_REG_MEM_FUNCTION(3) | /* equal */
> + WAIT_REG_MEM_ENGINE(eng_sel)));
> +
> + WARN_ON(mem_space && addr0 & 0x3); /* Dword align */
> + amdgpu_ring_write(ring, addr0);
> + amdgpu_ring_write(ring, addr1);
> + amdgpu_ring_write(ring, ref);
> + amdgpu_ring_write(ring, mask);
> + amdgpu_ring_write(ring, inv); /* poll interval */
> +}
> +
> +static void gfx_v8_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
> + uint32_t val, uint32_t mask)
> +{
> + gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
> +}
> +
> static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
> {
> int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> uint32_t seq = ring->fence_drv.sync_seq;
> uint64_t addr = ring->fence_drv.gpu_addr;
>
> + gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);
> + amdgpu_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);
> + amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
> + ring->fence_drv.sync_seq,
> + AMDGPU_FENCE_FLAG_EXEC);
> +
> amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
> amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
> WAIT_REG_MEM_FUNCTION(3) | /* equal */
> @@ -6400,46 +6433,6 @@ static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
> amdgpu_ring_write(ring, val);
> }
>
> -static void gfx_v8_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
> - int mem_space, int opt, uint32_t addr0,
> - uint32_t addr1, uint32_t ref, uint32_t mask,
> - uint32_t inv)
> -{
> - amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
> - amdgpu_ring_write(ring,
> - /* memory (1) or register (0) */
> - (WAIT_REG_MEM_MEM_SPACE(mem_space) |
> - WAIT_REG_MEM_OPERATION(opt) | /* wait */
> - WAIT_REG_MEM_FUNCTION(3) | /* equal */
> - WAIT_REG_MEM_ENGINE(eng_sel)));
> -
> - if (mem_space)
> - BUG_ON(addr0 & 0x3); /* Dword align */
> - amdgpu_ring_write(ring, addr0);
> - amdgpu_ring_write(ring, addr1);
> - amdgpu_ring_write(ring, ref);
> - amdgpu_ring_write(ring, mask);
> - amdgpu_ring_write(ring, inv); /* poll interval */
> -}
> -
> -static void gfx_v8_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
> - uint32_t val, uint32_t mask)
> -{
> - gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
> -}
> -
> -static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
> -{
> - struct amdgpu_device *adev = ring->adev;
> - uint32_t value = 0;
> -
> - value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
> - value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
> - value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
> - value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
> - WREG32(mmSQ_CMD, value);
> -}
> -
> static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
> enum amdgpu_interrupt_state state)
> {
> @@ -6936,14 +6929,13 @@ static int gfx_v8_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
> if (r)
> return r;
>
> - if (amdgpu_ring_alloc(ring, 7 + 12 + 5))
> + if (amdgpu_ring_alloc(ring, 7 + 12 + 5 + 7))
> return -ENOMEM;
> - gfx_v8_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr,
> - ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC);
> - gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);
> - gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);
>
> - return amdgpu_ring_test_ring(ring);
> + gfx_v8_0_ring_emit_pipeline_sync(ring);
> + amdgpu_ring_commit(ring);
> +
> + return gfx_v8_0_ring_test_ib(ring, AMDGPU_QUEUE_RESET_TIMEOUT);
> }
>
> static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
> @@ -7009,7 +7001,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
> .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
> .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
> .emit_wreg = gfx_v8_0_ring_emit_wreg,
> - .soft_recovery = gfx_v8_0_ring_soft_recovery,
> .emit_mem_sync = gfx_v8_0_emit_mem_sync,
> .reset = gfx_v8_0_reset_kgq,
> };
> @@ -7044,7 +7035,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
> .insert_nop = amdgpu_ring_insert_nop,
> .pad_ib = amdgpu_ring_generic_pad_ib,
> .emit_wreg = gfx_v8_0_ring_emit_wreg,
> - .soft_recovery = gfx_v8_0_ring_soft_recovery,
Same comment here.
Alex
> .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
> .emit_wave_limit = gfx_v8_0_emit_wave_limit,
> };
> --
> 2.34.1
>
