[Public]
Hi all,
This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.
APU
* Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
* Thunderbolt -> LG Ultrafine 5k
* MST DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 2x 4k60hz displays
* USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
* SST PCON -> Club3D CAC-1085 + 1x 4k 144hz, FRL3, at a max resolution supported by the dongle of 4k 120hz YUV420 12bpc.
* MST PCON -> 1x 4k 144hz, FRL3, at a max resolution supported by the adapter of 4k 120hz RGB 8bpc.
DGPU
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multiple Display DP -> 4k240hz + 4k144hz
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
* MST DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
* Changing display configurations and settings
* Video/Audio playback
* Benchmark testing
* Suspend/Resume testing
* Feature testing (Freesync, HDCP, etc.)
Automated testing includes (but is not limited to)
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The testing is mainly tested on the following displays, but occasionally there are tests with other displays
* Samsung G8 Neo 4k240hz
* Samsung QN55QN95B 4k 120hz
* Acer XV322QKKV 4k144hz
* HP U27 4k Wireless 4k60hz
* LG 27UD58B 4k60hz
* LG 32UN650WA 4k60hz
* LG Ultrafine 5k 5k60hz
* AU Optronics B140HAN01.1 1080p 60hz eDP
* AU Optronics B160UAN01.J 1920x1200 165hz eDP
* AU Optronics B160QAN02.L 2560x1600 120hz eDP
The patchset consists of the amd-staging-drm-next branch (Head commit - b00449dc8724d2c6f924f1954bdab911afdfce02 drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6) with new patches added on top of it.
Tested on Ubuntu 24.04.1, on Wayland and X11, using KDE Plasma and Gnome.
Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
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1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
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-----Original Message-----
From: Mohamed, Zaeem <Zaeem.Mohamed@xxxxxxx>
Sent: Tuesday, January 21, 2025 2:39 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Lin, Wayne <Wayne.Lin@xxxxxxx>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@xxxxxxx>; Zuo, Jerry <Jerry.Zuo@xxxxxxx>; Mohamed, Zaeem <Zaeem.Mohamed@xxxxxxx>; Chiu, Solomon <Solomon.Chiu@xxxxxxx>; Wheeler, Daniel <Daniel.Wheeler@xxxxxxx>
Subject: [PATCH 00/14] DC Patches JANUARY 20, 2025
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fixes on psr_version, dcn35 register address, DCPG OP control sequences
- Imporvements to CR AUX RD interval interpretation, dio link encoder
- Disable PSR-SU on some OLED panels
Cc: Daniel Wheeler <daniel.wheeler@xxxxxxx>
Alex Hung (1):
drm/amd/display: Fix possible NULL dereferencing
Aric Cyr (1):
drm/amd/display: 3.2.318
Austin Zheng (1):
drm/amd/display: Account For OTO Prefetch Bandwidth When Calculating
Urgent Bandwidth
Charlene Liu (1):
drm/amd/display: pass calculated dram_speed_mts to dml2
Dillon Varone (1):
drm/amd/display: Ammend DCPG IP control sequences to align with HW
guidance
George Shen (1):
drm/amd/display: Update CR AUX RD interval interpretation
Hansen Dsouza (1):
drm/amd/display: Add boot option to reduce PHY SSC for HBR3
Peichen Huang (1):
drm/amd/display: refactor dio link encoder assigning
Sung Lee (1):
drm/amd/display: Guard Possible Null Pointer Dereference
Tom Chung (2):
drm/amd/display: Initial psr_version with correct setting
drm/amd/display: Disable PSR-SU on some OLED panel
Wayne Lin (1):
drm/amd/display: Fix potential NULL dereference
Zhikai Zhai (1):
drm/amd/display: Update Cursor request mode to the beginning prefetch
always
loanchen (1):
drm/amd/display: Correct register address in dcn35
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 20 ++
.../drm/amd/display/dc/bios/bios_parser2.c | 4 +-
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 202 +++++++++++++++++-
drivers/gpu/drm/amd/display/dc/dc.h | 4 +-
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 +
.../amd/display/dc/dml/dcn351/dcn351_fpu.c | 1 +
.../src/dml2_core/dml2_core_dcn4_calcs.c | 25 ++-
.../src/dml2_core/dml2_core_shared_types.h | 5 +
.../display/dc/dml2/dml2_translation_helper.c | 9 +-
.../drm/amd/display/dc/dml2/dml2_wrapper.h | 1 +
.../amd/display/dc/hubp/dcn31/dcn31_hubp.c | 2 +-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 22 +-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 14 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 34 +++
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 3 +
.../amd/display/dc/hwss/dcn401/dcn401_init.c | 2 +-
.../gpu/drm/amd/display/dc/inc/core_types.h | 3 +
.../link/protocols/link_dp_training_8b_10b.c | 7 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 +
21 files changed, 339 insertions(+), 35 deletions(-)
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2.34.1
