On Fri, Jan 17, 2025 at 10:14 AM Lijo Lazar <lijo.lazar@xxxxxxx> wrote:
>
> Fix the initialization and usage of capability values and mask.
> SMU_CAPS_MASK indicates mask value, and SMU_CAPS represent the
> capability value.
>
Might be cleaner to have CAP_GET and CAP_SET macros.
Alex
> Signed-off-by: Lijo Lazar <lijo.lazar@xxxxxxx>
>
> Fixes: 9bb53d2ce109 ("drm/amd/pm: Add capability flags for SMU v13.0.6")
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 80 ++++++++++---------
> 1 file changed, 42 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index 56e26fcd3066..52fd8355eee1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -118,8 +118,9 @@ enum smu_v13_0_6_caps {
> SMU_13_0_6_CAPS_ALL,
> };
>
> -#define SMU_CAPS_MASK(x) (ULL(1) << x)
> -#define SMU_CAPS(x) SMU_CAPS_MASK(SMU_13_0_6_CAPS_##x)
> +#define SMU_CAPS_TO_MASK(x) (ULL(1) << x)
> +#define SMU_CAPS(x) SMU_13_0_6_CAPS_##x
> +#define SMU_CAPS_MASK(x) SMU_CAPS_TO_MASK(SMU_CAPS(x))
>
> struct mca_bank_ipid {
> enum amdgpu_mca_ip ip;
> @@ -287,82 +288,84 @@ struct smu_v13_0_6_dpm_map {
> static void smu_v13_0_14_init_caps(struct smu_context *smu)
> {
> struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> - uint64_t caps = SMU_CAPS(DPM) | SMU_CAPS(UNI_METRICS) |
> - SMU_CAPS(SET_UCLK_MAX) | SMU_CAPS(DPM_POLICY) |
> - SMU_CAPS(PCIE_METRICS) | SMU_CAPS(CTF_LIMIT) |
> - SMU_CAPS(MCA_DEBUG_MODE) | SMU_CAPS(RMA_MSG) |
> - SMU_CAPS(ACA_SYND);
> + uint64_t caps = SMU_CAPS_MASK(DPM) | SMU_CAPS_MASK(UNI_METRICS) |
> + SMU_CAPS_MASK(SET_UCLK_MAX) |
> + SMU_CAPS_MASK(DPM_POLICY) |
> + SMU_CAPS_MASK(PCIE_METRICS) | SMU_CAPS_MASK(CTF_LIMIT) |
> + SMU_CAPS_MASK(MCA_DEBUG_MODE) | SMU_CAPS_MASK(RMA_MSG) |
> + SMU_CAPS_MASK(ACA_SYND);
> uint32_t fw_ver = smu->smc_fw_version;
>
> if (fw_ver >= 0x05550E00)
> - caps |= SMU_CAPS(OTHER_END_METRICS);
> + caps |= SMU_CAPS_MASK(OTHER_END_METRICS);
> if (fw_ver >= 0x05551000)
> - caps |= SMU_CAPS(HST_LIMIT_METRICS);
> + caps |= SMU_CAPS_MASK(HST_LIMIT_METRICS);
> if (fw_ver >= 0x05550B00)
> - caps |= SMU_CAPS(PER_INST_METRICS);
> + caps |= SMU_CAPS_MASK(PER_INST_METRICS);
> if (fw_ver > 0x05550f00)
> - caps |= SMU_CAPS(SDMA_RESET);
> + caps |= SMU_CAPS_MASK(SDMA_RESET);
>
> dpm_context->caps = caps;
> }
>
> static void smu_v13_0_6_init_caps(struct smu_context *smu)
> {
> - uint64_t caps = SMU_CAPS(DPM) | SMU_CAPS(UNI_METRICS) |
> - SMU_CAPS(SET_UCLK_MAX) | SMU_CAPS(DPM_POLICY) |
> - SMU_CAPS(PCIE_METRICS) | SMU_CAPS(MCA_DEBUG_MODE) |
> - SMU_CAPS(CTF_LIMIT) | SMU_CAPS(RMA_MSG) |
> - SMU_CAPS(ACA_SYND);
> + uint64_t caps =
> + SMU_CAPS_MASK(DPM) | SMU_CAPS_MASK(UNI_METRICS) |
> + SMU_CAPS_MASK(SET_UCLK_MAX) | SMU_CAPS_MASK(DPM_POLICY) |
> + SMU_CAPS_MASK(PCIE_METRICS) | SMU_CAPS_MASK(MCA_DEBUG_MODE) |
> + SMU_CAPS_MASK(CTF_LIMIT) | SMU_CAPS_MASK(RMA_MSG) |
> + SMU_CAPS_MASK(ACA_SYND);
> struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> struct amdgpu_device *adev = smu->adev;
> uint32_t fw_ver = smu->smc_fw_version;
> uint32_t pgm = (fw_ver >> 24) & 0xFF;
>
> if (fw_ver < 0x552F00)
> - caps &= ~SMU_CAPS(DPM);
> + caps &= ~SMU_CAPS_MASK(DPM);
>
> if (adev->flags & AMD_IS_APU) {
> - caps &= ~SMU_CAPS(PCIE_METRICS);
> - caps &= ~SMU_CAPS(SET_UCLK_MAX);
> - caps &= ~SMU_CAPS(DPM_POLICY);
> - caps &= ~SMU_CAPS(RMA_MSG);
> - caps &= ~SMU_CAPS(ACA_SYND);
> + caps &= ~SMU_CAPS_MASK(PCIE_METRICS);
> + caps &= ~SMU_CAPS_MASK(SET_UCLK_MAX);
> + caps &= ~SMU_CAPS_MASK(DPM_POLICY);
> + caps &= ~SMU_CAPS_MASK(RMA_MSG);
> + caps &= ~SMU_CAPS_MASK(ACA_SYND);
>
> if (fw_ver <= 0x4556900)
> - caps &= ~SMU_CAPS(UNI_METRICS);
> + caps &= ~SMU_CAPS_MASK(UNI_METRICS);
>
> if (fw_ver >= 0x04556F00)
> - caps |= SMU_CAPS(HST_LIMIT_METRICS);
> + caps |= SMU_CAPS_MASK(HST_LIMIT_METRICS);
> if (fw_ver >= 0x04556A00)
> - caps |= SMU_CAPS(PER_INST_METRICS);
> + caps |= SMU_CAPS_MASK(PER_INST_METRICS);
> if (fw_ver < 0x554500)
> - caps &= ~SMU_CAPS(CTF_LIMIT);
> + caps &= ~SMU_CAPS_MASK(CTF_LIMIT);
> } else {
> if (fw_ver >= 0x557600)
> - caps |= SMU_CAPS(OTHER_END_METRICS);
> + caps |= SMU_CAPS_MASK(OTHER_END_METRICS);
> if (fw_ver < 0x00556000)
> - caps &= ~SMU_CAPS(DPM_POLICY);
> + caps &= ~SMU_CAPS_MASK(DPM_POLICY);
> if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
> - caps &= ~SMU_CAPS(SET_UCLK_MAX);
> + caps &= ~SMU_CAPS_MASK(SET_UCLK_MAX);
> if (fw_ver < 0x556300)
> - caps &= ~SMU_CAPS(PCIE_METRICS);
> + caps &= ~SMU_CAPS_MASK(PCIE_METRICS);
> if (fw_ver < 0x554800)
> - caps &= ~SMU_CAPS(MCA_DEBUG_MODE);
> + caps &= ~SMU_CAPS_MASK(MCA_DEBUG_MODE);
> if (fw_ver >= 0x556F00)
> - caps |= SMU_CAPS(PER_INST_METRICS);
> + caps |= SMU_CAPS_MASK(PER_INST_METRICS);
> if (fw_ver < 0x554500)
> - caps &= ~SMU_CAPS(CTF_LIMIT);
> + caps &= ~SMU_CAPS_MASK(CTF_LIMIT);
> if (fw_ver < 0x00555a00)
> - caps &= ~SMU_CAPS(RMA_MSG);
> + caps &= ~SMU_CAPS_MASK(RMA_MSG);
> if (fw_ver < 0x00555600)
> - caps &= ~SMU_CAPS(ACA_SYND);
> + caps &= ~SMU_CAPS_MASK(ACA_SYND);
> if (pgm == 0 && fw_ver >= 0x557900)
> - caps |= SMU_CAPS(HST_LIMIT_METRICS);
> + caps |= SMU_CAPS_MASK(HST_LIMIT_METRICS);
> }
> if (((pgm == 7) && (fw_ver > 0x07550700)) ||
> ((pgm == 0) && (fw_ver > 0x00557700)) ||
> ((pgm == 4) && (fw_ver > 0x4556e6c)))
> - caps |= SMU_CAPS(SDMA_RESET);
> + caps |= SMU_CAPS_MASK(SDMA_RESET);
>
> dpm_context->caps = caps;
> }
> @@ -372,7 +375,8 @@ static inline bool smu_v13_0_6_caps_supported(struct smu_context *smu,
> {
> struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
>
> - return (dpm_context->caps & SMU_CAPS_MASK(caps)) == SMU_CAPS_MASK(caps);
> + return (dpm_context->caps & SMU_CAPS_TO_MASK(caps)) ==
> + SMU_CAPS_TO_MASK(caps);
> }
>
> static void smu_v13_0_x_init_caps(struct smu_context *smu)
> --
> 2.25.1
>
