Add RRMT control register offset for VCN v4.0.3 Signed-off-by: Lijo Lazar <lijo.lazar@xxxxxxx> Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@xxxxxxx> --- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h index e9742d10de1c..a0e27aefb56d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h @@ -779,7 +779,8 @@ #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 #define regVCN_RAS_CNTL 0x02df #define regVCN_RAS_CNTL_BASE_IDX 1 - +#define regVCN_RRMT_CNTL 0x0940 +#define regVCN_RRMT_CNTL_BASE_IDX 1 // addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec // base address: 0x20f00 -- 2.25.1
