[AMD Official Use Only - AMD Internal Distribution Only]
Hi Tim
-----Original Message-----
From: Huang, Tim <Tim.Huang@xxxxxxx>
Sent: Monday, December 16, 2024 4:29 PM
To: Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Zhu, Jiadong <Jiadong.Zhu@xxxxxxx>; Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>; Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>
Subject: RE: [PATCH 3/3] drm/amdgpu/pm: Implement SDMA queue for different asic
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -----Original Message-----
> From: Jesse.zhang@xxxxxxx <jesse.zhang@xxxxxxx>
> Sent: Friday, December 13, 2024 7:41 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian
> <Christian.Koenig@xxxxxxx>; Zhu, Jiadong <Jiadong.Zhu@xxxxxxx>; Huang,
> Tim <Tim.Huang@xxxxxxx>; Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>;
> Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>
> Subject: [PATCH 3/3] drm/amdgpu/pm: Implement SDMA queue for different
> asic
Here missed a "reset" for the subject?
>
> From: "Jesse.zhang@xxxxxxx" <Jesse.zhang@xxxxxxx>
>
> Implement sdma queue reset by SMU_MSG_ResetSDMA2.
>
> Signed-off-by: Jesse Zhang <jesse.zhang@xxxxxxx>
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28
> ++++++++++++++-----
> 1 file changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index 9222e7a777a6..e57d83099f4c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -2724,14 +2724,28 @@ static int smu_v13_0_6_reset_sdma(struct
> smu_context *smu, uint32_t inst_mask)
> struct amdgpu_device *adev = smu->adev;
> int ret = 0;
>
> - /* the message is only valid on SMU 13.0.6 with pmfw 85.121.00 and
> above */
> - if ((adev->flags & AMD_IS_APU) ||
> - amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6) ||
> - smu->smc_fw_version < 0x00557900)
> - return 0;
> + switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
> + case IP_VERSION(13, 0, 6):
> + if (((smu->smc_fw_version > 0x07550763) &&
> + (smu->smc_fw_version < 0x080000000)) ||
> + ((smu->smc_fw_version > 0x00557700) &&
> + (smu->smc_fw_version < 0x01000000)))
Just curious why there're two ranges, Are they intended for two different ASICs?
Yes, I will update the patch according to our offline discussion.
Tim
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_ResetSDMA, inst_mask, NULL);
> + else if ((adev->flags & AMD_IS_APU) &&
> + (smu->smc_fw_version > 0x4556e6c))
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_ResetSDMA2, inst_mask, NULL);
> + break;
> + case IP_VERSION(13, 0, 14):
> + if (smu->smc_fw_version > 0x05550f00)
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_ResetSDMA2, inst_mask, NULL);
> + break;
> + default:
> + break;
> + }
>
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> - SMU_MSG_ResetSDMA, inst_mask, NULL);
> if (ret)
> dev_err(smu->adev->dev,
> "failed to send ResetSDMA event with mask
> 0x%x\n",
> --
> 2.25.1
