The kiq's srbm window is independent of the MMIO srbm window.
Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 34 +++++++++++++++---------------
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vi.c | 9 ++++++--
drivers/gpu/drm/amd/amdgpu/vi.h | 2 +-
7 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 50bfead..9ffe1d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -942,6 +942,7 @@ struct amdgpu_kiq {
struct amdgpu_irq_src irq;
uint32_t reg_val_offs;
spinlock_t ring_lock;
+ spinlock_t srbm_lock;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3469b9d..4c8ec52 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1925,6 +1925,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
spin_lock_init(&adev->audio_endpt_idx_lock);
spin_lock_init(&adev->mm_stats.lock);
spin_lock_init(&adev->gfx.kiq.ring_lock);
+ spin_lock_init(&adev->gfx.kiq.srbm_lock);
INIT_LIST_HEAD(&adev->shadow_list);
mutex_init(&adev->shadow_list_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 976ee0b..be40fc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3948,14 +3948,14 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
mutex_lock(&adev->srbm_mutex);
for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
- vi_srbm_select(adev, 0, 0, 0, i);
+ vi_srbm_select(adev, 0, 0, 0, i, false);
/* CP and shaders */
WREG32(mmSH_MEM_CONFIG, sh_mem_config);
WREG32(mmSH_MEM_APE1_BASE, 1);
WREG32(mmSH_MEM_APE1_LIMIT, 0);
WREG32(mmSH_MEM_BASES, sh_mem_bases);
}
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
}
@@ -3997,7 +3997,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
INDEX_STRIDE, 3);
mutex_lock(&adev->srbm_mutex);
for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
- vi_srbm_select(adev, 0, 0, 0, i);
+ vi_srbm_select(adev, 0, 0, 0, i, false);
/* CP and shaders */
if (i == 0) {
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
@@ -4020,7 +4020,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
WREG32(mmSH_MEM_APE1_LIMIT, 0);
WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
}
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
gfx_v8_0_init_compute_vmid(adev);
@@ -5098,18 +5098,18 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0, false);
r = gfx_v8_0_deactivate_hqd(adev, 1);
if (r) {
dev_err(adev->dev, "failed to deactivate ring %s\n", ring->name);
goto out_unlock;
}
gfx_v8_0_mqd_commit(adev, mqd);
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
} else {
mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0, false);
gfx_v8_0_mqd_init(ring);
r = gfx_v8_0_deactivate_hqd(adev, 1);
if (r) {
@@ -5117,7 +5117,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
goto out_unlock;
}
gfx_v8_0_mqd_commit(adev, mqd);
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
if (adev->gfx.mec.mqd_backup[mqd_idx])
@@ -5127,7 +5127,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
return r;
out_unlock:
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
return r;
}
@@ -5140,9 +5140,9 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0, false);
gfx_v8_0_mqd_init(ring);
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
if (adev->gfx.mec.mqd_backup[mqd_idx])
@@ -5473,9 +5473,9 @@ static int gfx_v8_0_pre_soft_reset(void *handle)
struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0, false);
gfx_v8_0_deactivate_hqd(adev, 2);
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
}
/* Disable MEC parsing/prefetching */
@@ -5573,9 +5573,9 @@ static int gfx_v8_0_post_soft_reset(void *handle)
struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0, false);
gfx_v8_0_deactivate_hqd(adev, 2);
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
}
gfx_v8_0_kiq_resume(adev);
@@ -6817,12 +6817,12 @@ static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
}
mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, me, pipe, 0, 0);
+ vi_srbm_select(adev, me, pipe, 0, 0, false);
WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE,
state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index f2d0710..0d0e432 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -424,12 +424,12 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
mutex_lock(&adev->srbm_mutex);
for (j = 0; j < 16; j++) {
- vi_srbm_select(adev, 0, 0, 0, j);
+ vi_srbm_select(adev, 0, 0, 0, j, false);
/* SDMA GFX */
WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
}
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index a69e5d4..05924a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -618,12 +618,12 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
mutex_lock(&adev->srbm_mutex);
for (j = 0; j < 16; j++) {
- vi_srbm_select(adev, 0, 0, 0, j);
+ vi_srbm_select(adev, 0, 0, 0, j, false);
/* SDMA GFX */
WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
}
- vi_srbm_select(adev, 0, 0, 0, 0);
+ vi_srbm_select(adev, 0, 0, 0, 0, false);
mutex_unlock(&adev->srbm_mutex);
WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 8217551..d9b7774 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -349,20 +349,25 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
* @pipe: pipe
* @queue: queue
* @vmid: VMID
+ * @kiq: edit MMIO or KIQ window
*
* Switches the currently active registers instances. Some
* registers are instanced per VMID, others are instanced per
* me/pipe/queue combination.
*/
void vi_srbm_select(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 queue, u32 vmid)
+ u32 me, u32 pipe, u32 queue, u32 vmid, bool kiq)
{
u32 srbm_gfx_cntl = 0;
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
- WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
+
+ if (kiq)
+ WREG32_KIQ_ASYNC(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
+ else
+ WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
}
static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 575d7ae..f5f3acb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -25,7 +25,7 @@
#define __VI_H__
void vi_srbm_select(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 queue, u32 vmid);
+ u32 me, u32 pipe, u32 queue, u32 vmid, bool kiq);
int vi_set_ip_blocks(struct amdgpu_device *adev);
#endif
--
2.9.3
