[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Yang Wang <kevinyang.wang@xxxxxxx>
Best Regards,
Kevin
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Kenneth Feng
Sent: Monday, November 18, 2024 16:01
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wang, Yang(Kevin) <KevinYang.Wang@xxxxxxx>; Feng, Kenneth <Kenneth.Feng@xxxxxxx>
Subject: [PATCH] drm/amd/pm: disable pcie speed switching on Intel platform for smu v14.0.2/3
disable pcie speed switching on Intel platform for smu v14.0.2/3 based on Intel's requirement.
Signed-off-by: Kenneth Feng <kenneth.feng@xxxxxxx>
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index 59b369eff30f..337d3312ef30 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -1472,6 +1472,14 @@ static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu,
if (pcie_table->pcie_lane[i] > pcie_width_cap)
pcie_table->pcie_lane[i] = pcie_width_cap;
+ if (i < pcie_table->num_of_link_levels - 1 &&
+ !(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
+ if (pcie_table->pcie_gen[i] < pcie_gen_cap)
+ pcie_table->pcie_gen[i] = pcie_gen_cap;
+ if (pcie_table->pcie_lane[i] < pcie_width_cap)
+ pcie_table->pcie_lane[i] = pcie_width_cap;
+ }
+
smu_pcie_arg = i << 16;
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
smu_pcie_arg |= pcie_table->pcie_lane[i];
--
2.34.1
