On Fri, Oct 25, 2024 at 1:13 AM <boyuan.zhang@xxxxxxx> wrote:
>
> From: Boyuan Zhang <boyuan.zhang@xxxxxxx>
>
> Perform set_powergating_state only for the instance of the current vcn
> IP block, instead of perform it for all vcn instances.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@xxxxxxx>
> Acked-by: Christian König <christian.koenig@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 313 ++++++++++++------------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 19 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 20 +-
> 6 files changed, 199 insertions(+), 213 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 34d94b09f04c..da3d55cc3ac1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -612,114 +612,111 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> *
> * Disable clock gating for VCN block
> */
> -static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
> +static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
> {
> uint32_t data;
> - int i;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> - /* UVD disable CGC */
> - data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
> - if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> - data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
> - else
> - data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
> - data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
> - data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
> - WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
> -
> - data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
> - data &= ~(UVD_CGC_GATE__SYS_MASK
> - | UVD_CGC_GATE__UDEC_MASK
> - | UVD_CGC_GATE__MPEG2_MASK
> - | UVD_CGC_GATE__REGS_MASK
> - | UVD_CGC_GATE__RBC_MASK
> - | UVD_CGC_GATE__LMI_MC_MASK
> - | UVD_CGC_GATE__LMI_UMC_MASK
> - | UVD_CGC_GATE__IDCT_MASK
> - | UVD_CGC_GATE__MPRD_MASK
> - | UVD_CGC_GATE__MPC_MASK
> - | UVD_CGC_GATE__LBSI_MASK
> - | UVD_CGC_GATE__LRBBM_MASK
> - | UVD_CGC_GATE__UDEC_RE_MASK
> - | UVD_CGC_GATE__UDEC_CM_MASK
> - | UVD_CGC_GATE__UDEC_IT_MASK
> - | UVD_CGC_GATE__UDEC_DB_MASK
> - | UVD_CGC_GATE__UDEC_MP_MASK
> - | UVD_CGC_GATE__WCB_MASK
> - | UVD_CGC_GATE__VCPU_MASK
> - | UVD_CGC_GATE__MMSCH_MASK);
> -
> - WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
> -
> - SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
> -
> - data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
> - data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
> - | UVD_CGC_CTRL__SYS_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_MODE_MASK
> - | UVD_CGC_CTRL__MPEG2_MODE_MASK
> - | UVD_CGC_CTRL__REGS_MODE_MASK
> - | UVD_CGC_CTRL__RBC_MODE_MASK
> - | UVD_CGC_CTRL__LMI_MC_MODE_MASK
> - | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
> - | UVD_CGC_CTRL__IDCT_MODE_MASK
> - | UVD_CGC_CTRL__MPRD_MODE_MASK
> - | UVD_CGC_CTRL__MPC_MODE_MASK
> - | UVD_CGC_CTRL__LBSI_MODE_MASK
> - | UVD_CGC_CTRL__LRBBM_MODE_MASK
> - | UVD_CGC_CTRL__WCB_MODE_MASK
> - | UVD_CGC_CTRL__VCPU_MODE_MASK
> - | UVD_CGC_CTRL__MMSCH_MODE_MASK);
> - WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
> -
> - /* turn on */
> - data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
> - data |= (UVD_SUVD_CGC_GATE__SRE_MASK
> - | UVD_SUVD_CGC_GATE__SIT_MASK
> - | UVD_SUVD_CGC_GATE__SMP_MASK
> - | UVD_SUVD_CGC_GATE__SCM_MASK
> - | UVD_SUVD_CGC_GATE__SDB_MASK
> - | UVD_SUVD_CGC_GATE__SRE_H264_MASK
> - | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
> - | UVD_SUVD_CGC_GATE__SIT_H264_MASK
> - | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
> - | UVD_SUVD_CGC_GATE__SCM_H264_MASK
> - | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
> - | UVD_SUVD_CGC_GATE__SDB_H264_MASK
> - | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
> - | UVD_SUVD_CGC_GATE__SCLR_MASK
> - | UVD_SUVD_CGC_GATE__UVD_SC_MASK
> - | UVD_SUVD_CGC_GATE__ENT_MASK
> - | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
> - | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
> - | UVD_SUVD_CGC_GATE__SITE_MASK
> - | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
> - | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
> - | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
> - | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
> - | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
> - WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
> -
> - data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
> - data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
> - WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
> + /* UVD disable CGC */
> + data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
> + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> + data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
> + else
> + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
> + data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
> + data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
> + WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
> +
> + data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
> + data &= ~(UVD_CGC_GATE__SYS_MASK
> + | UVD_CGC_GATE__UDEC_MASK
> + | UVD_CGC_GATE__MPEG2_MASK
> + | UVD_CGC_GATE__REGS_MASK
> + | UVD_CGC_GATE__RBC_MASK
> + | UVD_CGC_GATE__LMI_MC_MASK
> + | UVD_CGC_GATE__LMI_UMC_MASK
> + | UVD_CGC_GATE__IDCT_MASK
> + | UVD_CGC_GATE__MPRD_MASK
> + | UVD_CGC_GATE__MPC_MASK
> + | UVD_CGC_GATE__LBSI_MASK
> + | UVD_CGC_GATE__LRBBM_MASK
> + | UVD_CGC_GATE__UDEC_RE_MASK
> + | UVD_CGC_GATE__UDEC_CM_MASK
> + | UVD_CGC_GATE__UDEC_IT_MASK
> + | UVD_CGC_GATE__UDEC_DB_MASK
> + | UVD_CGC_GATE__UDEC_MP_MASK
> + | UVD_CGC_GATE__WCB_MASK
> + | UVD_CGC_GATE__VCPU_MASK
> + | UVD_CGC_GATE__MMSCH_MASK);
> +
> + WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
> +
> + SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
> +
> + data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
> + data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
> + | UVD_CGC_CTRL__SYS_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_MODE_MASK
> + | UVD_CGC_CTRL__MPEG2_MODE_MASK
> + | UVD_CGC_CTRL__REGS_MODE_MASK
> + | UVD_CGC_CTRL__RBC_MODE_MASK
> + | UVD_CGC_CTRL__LMI_MC_MODE_MASK
> + | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
> + | UVD_CGC_CTRL__IDCT_MODE_MASK
> + | UVD_CGC_CTRL__MPRD_MODE_MASK
> + | UVD_CGC_CTRL__MPC_MODE_MASK
> + | UVD_CGC_CTRL__LBSI_MODE_MASK
> + | UVD_CGC_CTRL__LRBBM_MODE_MASK
> + | UVD_CGC_CTRL__WCB_MODE_MASK
> + | UVD_CGC_CTRL__VCPU_MODE_MASK
> + | UVD_CGC_CTRL__MMSCH_MODE_MASK);
> + WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
> +
> + /* turn on */
> + data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
> + data |= (UVD_SUVD_CGC_GATE__SRE_MASK
> + | UVD_SUVD_CGC_GATE__SIT_MASK
> + | UVD_SUVD_CGC_GATE__SMP_MASK
> + | UVD_SUVD_CGC_GATE__SCM_MASK
> + | UVD_SUVD_CGC_GATE__SDB_MASK
> + | UVD_SUVD_CGC_GATE__SRE_H264_MASK
> + | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
> + | UVD_SUVD_CGC_GATE__SIT_H264_MASK
> + | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
> + | UVD_SUVD_CGC_GATE__SCM_H264_MASK
> + | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
> + | UVD_SUVD_CGC_GATE__SDB_H264_MASK
> + | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
> + | UVD_SUVD_CGC_GATE__SCLR_MASK
> + | UVD_SUVD_CGC_GATE__UVD_SC_MASK
> + | UVD_SUVD_CGC_GATE__ENT_MASK
> + | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
> + | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
> + | UVD_SUVD_CGC_GATE__SITE_MASK
> + | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
> + | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
> + | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
> + | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
> + | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
> + WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
> +
> + data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
> + data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
> + WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
> }
>
> static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
> @@ -777,59 +774,56 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
> *
> * Enable clock gating for VCN block
> */
> -static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
> +static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
> {
> uint32_t data = 0;
> - int i;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> - /* enable UVD CGC */
> - data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
> - if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> - data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
> - else
> - data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
> - data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
> - data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
> - WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
> -
> - data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
> - data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
> - | UVD_CGC_CTRL__SYS_MODE_MASK
> - | UVD_CGC_CTRL__UDEC_MODE_MASK
> - | UVD_CGC_CTRL__MPEG2_MODE_MASK
> - | UVD_CGC_CTRL__REGS_MODE_MASK
> - | UVD_CGC_CTRL__RBC_MODE_MASK
> - | UVD_CGC_CTRL__LMI_MC_MODE_MASK
> - | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
> - | UVD_CGC_CTRL__IDCT_MODE_MASK
> - | UVD_CGC_CTRL__MPRD_MODE_MASK
> - | UVD_CGC_CTRL__MPC_MODE_MASK
> - | UVD_CGC_CTRL__LBSI_MODE_MASK
> - | UVD_CGC_CTRL__LRBBM_MODE_MASK
> - | UVD_CGC_CTRL__WCB_MODE_MASK
> - | UVD_CGC_CTRL__VCPU_MODE_MASK);
> - WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
> -
> - data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
> - data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
> - | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
> - WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
> + /* enable UVD CGC */
> + data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
> + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> + data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
> + else
> + data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
> + data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
> + data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
> + WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
> +
> + data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
> + data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
> + | UVD_CGC_CTRL__SYS_MODE_MASK
> + | UVD_CGC_CTRL__UDEC_MODE_MASK
> + | UVD_CGC_CTRL__MPEG2_MODE_MASK
> + | UVD_CGC_CTRL__REGS_MODE_MASK
> + | UVD_CGC_CTRL__RBC_MODE_MASK
> + | UVD_CGC_CTRL__LMI_MC_MODE_MASK
> + | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
> + | UVD_CGC_CTRL__IDCT_MODE_MASK
> + | UVD_CGC_CTRL__MPRD_MODE_MASK
> + | UVD_CGC_CTRL__MPC_MODE_MASK
> + | UVD_CGC_CTRL__LBSI_MODE_MASK
> + | UVD_CGC_CTRL__LRBBM_MODE_MASK
> + | UVD_CGC_CTRL__WCB_MODE_MASK
> + | UVD_CGC_CTRL__VCPU_MODE_MASK);
> + WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
> +
> + data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
> + data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
> + | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
> + WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
> }
>
> static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
> @@ -1032,7 +1026,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev, unsigned int inst)
> return 0;
>
> /*SW clock gating */
> - vcn_v2_5_disable_clock_gating(adev);
> + vcn_v2_5_disable_clock_gating(adev, inst);
>
> if (adev->vcn.harvest_config & (1 << inst))
> return 0;
> @@ -1471,7 +1465,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev, unsigned int inst)
> /* clear status */
> WREG32_SOC15(VCN, inst, mmUVD_STATUS, 0);
>
> - vcn_v2_5_enable_clock_gating(adev);
> + vcn_v2_5_enable_clock_gating(adev, inst);
>
> /* enable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_POWER_STATUS),
> @@ -1794,6 +1788,7 @@ static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> {
> struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
> + int inst = ip_block->instance;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> @@ -1801,9 +1796,9 @@ static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> if (enable) {
> if (!vcn_v2_5_is_idle(adev))
> return -EBUSY;
> - vcn_v2_5_enable_clock_gating(adev);
> + vcn_v2_5_enable_clock_gating(adev, inst);
> } else {
> - vcn_v2_5_disable_clock_gating(adev);
> + vcn_v2_5_disable_clock_gating(adev, inst);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 451858f86272..b78c6da0a3cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2122,19 +2122,17 @@ static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> {
> struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> - int i;
> + int inst = ip_block->instance;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return 0;
>
> - if (enable) {
> - if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
> - return -EBUSY;
> - vcn_v3_0_enable_clock_gating(adev, i);
> - } else {
> - vcn_v3_0_disable_clock_gating(adev, i);
> - }
> + if (enable) {
> + if (RREG32_SOC15(VCN, inst, mmUVD_STATUS) != UVD_STATUS__IDLE)
> + return -EBUSY;
> + vcn_v3_0_enable_clock_gating(adev, inst);
> + } else {
> + vcn_v3_0_disable_clock_gating(adev, inst);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index fa7cf10e8900..8aa30a4bddbf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -1993,19 +1993,17 @@ static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> {
> struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> - int i;
> + int inst = ip_block->instance;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return 0;
>
> - if (enable) {
> - if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
> - return -EBUSY;
> - vcn_v4_0_enable_clock_gating(adev, i);
> - } else {
> - vcn_v4_0_disable_clock_gating(adev, i);
> - }
> + if (enable) {
> + if (RREG32_SOC15(VCN, inst, regUVD_STATUS) != UVD_STATUS__IDLE)
> + return -EBUSY;
> + vcn_v4_0_enable_clock_gating(adev, inst);
> + } else {
> + vcn_v4_0_disable_clock_gating(adev, inst);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index d05dcadb3e81..64b738f929b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1587,18 +1587,17 @@ static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> {
> struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> - int i;
> + int inst = ip_block->instance;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (enable) {
> - if (RREG32_SOC15(VCN, GET_INST(VCN, i),
> - regUVD_STATUS) != UVD_STATUS__IDLE)
> - return -EBUSY;
> - vcn_v4_0_3_enable_clock_gating(adev, i);
> - } else {
> - vcn_v4_0_3_disable_clock_gating(adev, i);
> - }
> + if (enable) {
> + if (RREG32_SOC15(VCN, GET_INST(VCN, inst),
> + regUVD_STATUS) != UVD_STATUS__IDLE)
> + return -EBUSY;
> + vcn_v4_0_3_enable_clock_gating(adev, inst);
> + } else {
> + vcn_v4_0_3_disable_clock_gating(adev, inst);
> }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 307c8e204456..c901255a05ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1490,19 +1490,17 @@ static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> {
> struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> - int i;
> + int inst = ip_block->instance;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return 0;
>
> - if (enable) {
> - if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
> - return -EBUSY;
> - vcn_v4_0_5_enable_clock_gating(adev, i);
> - } else {
> - vcn_v4_0_5_disable_clock_gating(adev, i);
> - }
> + if (enable) {
> + if (RREG32_SOC15(VCN, inst, regUVD_STATUS) != UVD_STATUS__IDLE)
> + return -EBUSY;
> + vcn_v4_0_5_enable_clock_gating(adev, inst);
> + } else {
> + vcn_v4_0_5_disable_clock_gating(adev, inst);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 50022bbb276e..6973fee37c12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1217,19 +1217,17 @@ static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> {
> struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> - int i;
> + int inst = ip_block->instance;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return 0;
>
> - if (enable) {
> - if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
> - return -EBUSY;
> - vcn_v5_0_0_enable_clock_gating(adev, i);
> - } else {
> - vcn_v5_0_0_disable_clock_gating(adev, i);
> - }
> + if (enable) {
> + if (RREG32_SOC15(VCN, inst, regUVD_STATUS) != UVD_STATUS__IDLE)
> + return -EBUSY;
> + vcn_v5_0_0_enable_clock_gating(adev, inst);
> + } else {
> + vcn_v5_0_0_disable_clock_gating(adev, inst);
> }
>
> return 0;
> --
> 2.34.1
>
