On Thu, Oct 24, 2024 at 11:03 PM <boyuan.zhang@xxxxxxx> wrote:
>
> From: Boyuan Zhang <boyuan.zhang@xxxxxxx>
>
> For vcn 4_0_5, add ip_block for each vcn instance during discovery stage.
>
> And only powering on/off one of the vcn instance using the
> instance value stored in ip_block, instead of powering on/off all
> vcn instances. Modify the existing functions to use the instance value
> in ip_block, and remove the original for loop for all vcn instances.
>
> v2: rename "i"/"j" to "inst" for instance value.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@xxxxxxx>
> Reviewed-by: Christian König <christian.koenig@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 510 +++++++++---------
> 2 files changed, 252 insertions(+), 261 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index ee10a9218df7..48160fa4d8ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -2358,7 +2358,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
> break;
> case IP_VERSION(4, 0, 5):
> case IP_VERSION(4, 0, 6):
> - amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
> + amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
> amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
> break;
> case IP_VERSION(5, 0, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 9c5257f370f2..0f3b25d3b9d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -132,7 +132,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_ring *ring;
> struct amdgpu_device *adev = ip_block->adev;
> - int i, r;
> + int inst = ip_block->instance, r;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
> uint32_t *ptr;
>
> @@ -146,57 +146,55 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> + volatile struct amdgpu_vcn4_fw_shared *fw_shared;
>
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> - atomic_set(&adev->vcn.inst[i].sched_score, 0);
> + atomic_set(&adev->vcn.inst[inst].sched_score, 0);
>
> - /* VCN UNIFIED TRAP */
> - r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
> - VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
> - if (r)
> - return r;
> + /* VCN UNIFIED TRAP */
> + r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
> + VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
> + if (r)
> + return r;
>
> - /* VCN POISON TRAP */
> - r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
> - VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
> - if (r)
> - return r;
> + /* VCN POISON TRAP */
> + r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
> + VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
> + if (r)
> + return r;
>
> - ring = &adev->vcn.inst[i].ring_enc[0];
> - ring->use_doorbell = true;
> - if (amdgpu_sriov_vf(adev))
> - ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> - i * (adev->vcn.num_enc_rings + 1) + 1;
> - else
> - ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> - 2 + 8 * i;
> - ring->vm_hub = AMDGPU_MMHUB0(0);
> - sprintf(ring->name, "vcn_unified_%d", i);
> -
> - r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
> - AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
> - if (r)
> - return r;
> + ring = &adev->vcn.inst[inst].ring_enc[0];
> + ring->use_doorbell = true;
> + if (amdgpu_sriov_vf(adev))
> + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> + inst * (adev->vcn.num_enc_rings + 1) + 1;
> + else
> + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> + 2 + 8 * inst;
> + ring->vm_hub = AMDGPU_MMHUB0(0);
> + sprintf(ring->name, "vcn_unified_%d", inst);
>
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
> - fw_shared->sq.is_enabled = 1;
> + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
> + AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
> + if (r)
> + return r;
>
> - fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
> - fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
> - AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
> + fw_shared->sq.is_enabled = 1;
>
> - if (amdgpu_sriov_vf(adev))
> - fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
> + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
> + fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
> + AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
>
> - if (amdgpu_vcnfw_log)
> - amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
> - }
> + if (amdgpu_sriov_vf(adev))
> + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
>
> + if (amdgpu_vcnfw_log)
> + amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
> +done:
> if (amdgpu_sriov_vf(adev)) {
> r = amdgpu_virt_alloc_mm_table(adev);
> if (r)
> @@ -992,180 +990,176 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
> *
> * Start VCN block
> */
> -static int vcn_v4_0_5_start(struct amdgpu_device *adev)
> +static int vcn_v4_0_5_start(struct amdgpu_device *adev, unsigned int inst)
> {
> volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> - int i, j, k, r;
> + int j, k, r;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->pm.dpm_enabled)
> - amdgpu_dpm_enable_vcn(adev, true, i);
> + if (adev->pm.dpm_enabled)
> + amdgpu_dpm_enable_vcn(adev, true, inst);
> +
> + if (adev->vcn.harvest_config & (1 << inst))
> + return 0;
> +
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> +
> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> + r = vcn_v4_0_5_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
> + return r;
> }
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + /* disable VCN power gating */
> + vcn_v4_0_5_disable_static_power_gating(adev, inst);
>
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> + /* set VCN status busy */
> + tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
> + WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
>
> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> - r = vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
> - continue;
> - }
> + /*SW clock gating */
> + vcn_v4_0_5_disable_clock_gating(adev, inst);
>
> - /* disable VCN power gating */
> - vcn_v4_0_5_disable_static_power_gating(adev, i);
> -
> - /* set VCN status busy */
> - tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
> - WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
> -
> - /*SW clock gating */
> - vcn_v4_0_5_disable_clock_gating(adev, i);
> -
> - /* enable VCPU clock */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
> - UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
> -
> - /* disable master interrupt */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
> - ~UVD_MASTINT_EN__VCPU_EN_MASK);
> -
> - /* enable LMI MC and UMC channels */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
> - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
> -
> - tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
> - tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
> - tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
> - WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
> -
> - /* setup regUVD_LMI_CTRL */
> - tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
> - WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
> - UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
> - UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
> - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
> - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
> -
> - /* setup regUVD_MPC_CNTL */
> - tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
> - tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
> - tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
> - WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
> -
> - /* setup UVD_MPC_SET_MUXA0 */
> - WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
> - ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
> - (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
> - (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
> - (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
> -
> - /* setup UVD_MPC_SET_MUXB0 */
> - WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
> - ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
> - (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
> - (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
> - (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
> -
> - /* setup UVD_MPC_SET_MUX */
> - WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
> - ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
> - (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> - (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
> -
> - vcn_v4_0_5_mc_resume(adev, i);
> -
> - /* VCN global tiling registers */
> - WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
> - adev->gfx.config.gb_addr_config);
> -
> - /* unblock VCPU register access */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
> - ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
> -
> - /* release VCPU reset to boot */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
> - ~UVD_VCPU_CNTL__BLK_RST_MASK);
> -
> - for (j = 0; j < 10; ++j) {
> - uint32_t status;
> -
> - for (k = 0; k < 100; ++k) {
> - status = RREG32_SOC15(VCN, i, regUVD_STATUS);
> - if (status & 2)
> - break;
> - mdelay(10);
> - if (amdgpu_emu_mode == 1)
> - msleep(1);
> - }
> + /* enable VCPU clock */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
> + UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
> +
> + /* disable master interrupt */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
> + ~UVD_MASTINT_EN__VCPU_EN_MASK);
> +
> + /* enable LMI MC and UMC channels */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
> + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
>
> - if (amdgpu_emu_mode == 1) {
> - r = -1;
> - if (status & 2) {
> - r = 0;
> - break;
> - }
> - } else {
> + tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
> + tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
> + tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
> + WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
> +
> + /* setup regUVD_LMI_CTRL */
> + tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
> + WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
> + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
> + UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
> + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
> + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
> +
> + /* setup regUVD_MPC_CNTL */
> + tmp = RREG32_SOC15(VCN, inst, regUVD_MPC_CNTL);
> + tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
> + tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
> + WREG32_SOC15(VCN, inst, regUVD_MPC_CNTL, tmp);
> +
> + /* setup UVD_MPC_SET_MUXA0 */
> + WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXA0,
> + ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
> + (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
> + (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
> + (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
> +
> + /* setup UVD_MPC_SET_MUXB0 */
> + WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXB0,
> + ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
> + (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
> + (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
> + (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
> +
> + /* setup UVD_MPC_SET_MUX */
> + WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUX,
> + ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
> + (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> + (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
> +
> + vcn_v4_0_5_mc_resume(adev, inst);
> +
> + /* VCN global tiling registers */
> + WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
> + adev->gfx.config.gb_addr_config);
> +
> + /* unblock VCPU register access */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
> + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
> +
> + /* release VCPU reset to boot */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
> + ~UVD_VCPU_CNTL__BLK_RST_MASK);
> +
> + for (j = 0; j < 10; ++j) {
> + uint32_t status;
> +
> + for (k = 0; k < 100; ++k) {
> + status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
> + if (status & 2)
> + break;
> + mdelay(10);
> + if (amdgpu_emu_mode == 1)
> + msleep(1);
> + }
> +
> + if (amdgpu_emu_mode == 1) {
> + r = -1;
> + if (status & 2) {
> r = 0;
> - if (status & 2)
> - break;
> -
> - dev_err(adev->dev,
> - "VCN[%d] is not responding, trying to reset VCPU!!!\n", i);
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
> - UVD_VCPU_CNTL__BLK_RST_MASK,
> - ~UVD_VCPU_CNTL__BLK_RST_MASK);
> - mdelay(10);
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
> + break;
> + }
> + } else {
> + r = 0;
> + if (status & 2)
> + break;
> +
> + dev_err(adev->dev,
> + "VCN[%d] is not responding, trying to reset VCPU!!!\n", inst);
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
> + UVD_VCPU_CNTL__BLK_RST_MASK,
> ~UVD_VCPU_CNTL__BLK_RST_MASK);
> + mdelay(10);
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
> + ~UVD_VCPU_CNTL__BLK_RST_MASK);
>
> - mdelay(10);
> - r = -1;
> - }
> + mdelay(10);
> + r = -1;
> }
> + }
>
> - if (r) {
> - dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
> - return r;
> - }
> + if (r) {
> + dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
> + return r;
> + }
>
> - /* enable master interrupt */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
> - UVD_MASTINT_EN__VCPU_EN_MASK,
> - ~UVD_MASTINT_EN__VCPU_EN_MASK);
> + /* enable master interrupt */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
> + UVD_MASTINT_EN__VCPU_EN_MASK,
> + ~UVD_MASTINT_EN__VCPU_EN_MASK);
>
> - /* clear the busy bit of VCN_STATUS */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
> - ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
> + /* clear the busy bit of VCN_STATUS */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
> + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
>
> - ring = &adev->vcn.inst[i].ring_enc[0];
> - WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
> - ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> - VCN_RB1_DB_CTRL__EN_MASK);
> -
> - WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
> - WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> - WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
> -
> - tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
> - tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
> - WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
> - fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
> - WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
> - WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
> -
> - tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
> - WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
> - ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
> -
> - tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
> - tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
> - WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
> - fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
> - }
> + ring = &adev->vcn.inst[inst].ring_enc[0];
> + WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
> + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> + VCN_RB1_DB_CTRL__EN_MASK);
> +
> + WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
> + WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> + WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
> +
> + tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
> + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
> + WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
> + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
> + WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
> + WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
> +
> + tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
> + WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
> + ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
> +
> + tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
> + tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
> + WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
> + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
>
> return 0;
> }
> @@ -1205,83 +1199,79 @@ static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
> *
> * Stop VCN block
> */
> -static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
> +static int vcn_v4_0_5_stop(struct amdgpu_device *adev, unsigned int inst)
> {
> volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> uint32_t tmp;
> - int i, r = 0;
> + int r = 0;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> -
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> - vcn_v4_0_5_stop_dpg_mode(adev, i);
> - continue;
> - }
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
>
> - /* wait for vcn idle */
> - r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
> - if (r)
> - return r;
> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> + vcn_v4_0_5_stop_dpg_mode(adev, inst);
> + goto done;
> + }
>
> - tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
> - UVD_LMI_STATUS__READ_CLEAN_MASK |
> - UVD_LMI_STATUS__WRITE_CLEAN_MASK |
> - UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
> - r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
> - if (r)
> - return r;
> + /* wait for vcn idle */
> + r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
> + if (r)
> + return r;
>
> - /* disable LMI UMC channel */
> - tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
> - tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
> - WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
> - tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
> - UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
> - r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
> - if (r)
> - return r;
> + tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
> + UVD_LMI_STATUS__READ_CLEAN_MASK |
> + UVD_LMI_STATUS__WRITE_CLEAN_MASK |
> + UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
> + r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
> + if (r)
> + return r;
>
> - /* block VCPU register access */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
> - UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
> - ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
> + /* disable LMI UMC channel */
> + tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
> + tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
> + WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
> + tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
> + UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
> + r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
> + if (r)
> + return r;
>
> - /* reset VCPU */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
> - UVD_VCPU_CNTL__BLK_RST_MASK,
> - ~UVD_VCPU_CNTL__BLK_RST_MASK);
> + /* block VCPU register access */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
> + UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
> + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
>
> - /* disable VCPU clock */
> - WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
> - ~(UVD_VCPU_CNTL__CLK_EN_MASK));
> + /* reset VCPU */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
> + UVD_VCPU_CNTL__BLK_RST_MASK,
> + ~UVD_VCPU_CNTL__BLK_RST_MASK);
>
> - /* apply soft reset */
> - tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
> - tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
> - WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
> - tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
> - tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
> - WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
> + /* disable VCPU clock */
> + WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
> + ~(UVD_VCPU_CNTL__CLK_EN_MASK));
>
> - /* clear status */
> - WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
> + /* apply soft reset */
> + tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
> + tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
> + WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
> + tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
> + tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
> + WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
>
> - /* apply HW clock gating */
> - vcn_v4_0_5_enable_clock_gating(adev, i);
> + /* clear status */
> + WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
>
> - /* enable VCN power gating */
> - vcn_v4_0_5_enable_static_power_gating(adev, i);
> - }
> + /* apply HW clock gating */
> + vcn_v4_0_5_enable_clock_gating(adev, inst);
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - if (adev->pm.dpm_enabled)
> - amdgpu_dpm_enable_vcn(adev, false, i);
> - }
> + /* enable VCN power gating */
> + vcn_v4_0_5_enable_static_power_gating(adev, inst);
> +done:
> + if (adev->pm.dpm_enabled)
> + amdgpu_dpm_enable_vcn(adev, false, inst);
>
> return 0;
> }
> @@ -1542,9 +1532,9 @@ static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> return 0;
>
> if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v4_0_5_stop(adev);
> + ret = vcn_v4_0_5_stop(adev, inst);
> else
> - ret = vcn_v4_0_5_start(adev);
> + ret = vcn_v4_0_5_start(adev, inst);
>
> if (!ret)
> adev->vcn.inst[inst].cur_state = state;
> --
> 2.34.1
>
