On Fri, Oct 25, 2024 at 12:53 AM <boyuan.zhang@xxxxxxx> wrote:
>
> From: Boyuan Zhang <boyuan.zhang@xxxxxxx>
>
> Move all per instance variables from amdgpu_vcn to amdgpu_vcn_inst.
>
> Move adev->vcn.fw[i] from amdgpu_vcn to amdgpu_vcn_inst.
> Move adev->vcn.vcn_config[i] from amdgpu_vcn to amdgpu_vcn_inst.
> Move adev->vcn.vcn_codec_disable_mask[i] from amdgpu_vcn to amdgpu_vcn_inst.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@xxxxxxx>
> Reviewed-by: Christian König <christian.koenig@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 20 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++--
> 11 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 73f4d56c5de4..cce3f1a6f288 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1340,7 +1340,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> */
> if (adev->vcn.num_vcn_inst <
> AMDGPU_MAX_VCN_INSTANCES) {
> - adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
> + adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
> ip->revision & 0xc0;
> adev->vcn.num_vcn_inst++;
> adev->vcn.inst_mask |=
> @@ -1705,7 +1705,7 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
> * so this won't overflow.
> */
> for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
> - adev->vcn.vcn_codec_disable_mask[v] =
> + adev->vcn.inst[v].vcn_codec_disable_mask =
> le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
> }
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index aecb78e0519f..49802e66a358 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -99,11 +99,11 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev)
> amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
> for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
> - r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s_%d.bin", ucode_prefix, i);
> + r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s_%d.bin", ucode_prefix, i);
> else
> - r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s.bin", ucode_prefix);
> + r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s.bin", ucode_prefix);
> if (r) {
> - amdgpu_ucode_release(&adev->vcn.fw[i]);
> + amdgpu_ucode_release(&adev->vcn.inst[i].fw);
> return r;
> }
> }
> @@ -151,7 +151,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> adev->vcn.using_unified_queue =
> amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0);
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[0]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[0].fw->data;
> adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
>
> /* Bit 20-23, it is encode major and non-zero for new naming convention.
> @@ -270,7 +270,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
> for (i = 0; i < adev->vcn.num_enc_rings; ++i)
> amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
>
> - amdgpu_ucode_release(&adev->vcn.fw[j]);
> + amdgpu_ucode_release(&adev->vcn.inst[j].fw);
> }
>
> mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
> @@ -282,7 +282,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
> bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
> {
> bool ret = false;
> - int vcn_config = adev->vcn.vcn_config[vcn_instance];
> + int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;
>
> if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
> ret = true;
> @@ -362,12 +362,12 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
> const struct common_firmware_header *hdr;
> unsigned int offset;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> memcpy_toio(adev->vcn.inst[i].cpu_addr,
> - adev->vcn.fw[i]->data + offset,
> + adev->vcn.inst[i].fw->data + offset,
> le32_to_cpu(hdr->ucode_size_bytes));
> drm_dev_exit(idx);
> }
> @@ -1063,7 +1063,7 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
> if (adev->vcn.harvest_config & (1 << i))
> continue;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
> /* currently only support 2 FW instances */
> if (i >= 2) {
> dev_info(adev->dev, "More then 2 VCN FW instances!\n");
> @@ -1071,7 +1071,7 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
> }
> idx = AMDGPU_UCODE_ID_VCN + i;
> adev->firmware.ucode[idx].ucode_id = idx;
> - adev->firmware.ucode[idx].fw = adev->vcn.fw[i];
> + adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 765b809d48a2..ba58b4f07643 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -297,6 +297,9 @@ struct amdgpu_vcn_inst {
> atomic_t dpg_enc_submission_cnt;
> struct amdgpu_vcn_fw_shared fw_shared;
> uint8_t aid_id;
> + const struct firmware *fw; /* VCN firmware */
> + uint8_t vcn_config;
> + uint32_t vcn_codec_disable_mask;
> };
>
> struct amdgpu_vcn_ras {
> @@ -306,15 +309,12 @@ struct amdgpu_vcn_ras {
> struct amdgpu_vcn {
> unsigned fw_version;
> struct delayed_work idle_work;
> - const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */
> unsigned num_enc_rings;
> enum amd_powergating_state cur_state;
> bool indirect_sram;
>
> uint8_t num_vcn_inst;
> struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
> - uint8_t vcn_config[AMDGPU_MAX_VCN_INSTANCES];
> - uint32_t vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];
> struct amdgpu_vcn_reg internal;
> struct mutex vcn_pg_lock;
> struct mutex vcn1_jpeg1_workaround;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 00d9fdd2869e..5ea96c983517 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -345,7 +345,7 @@ static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)
> */
> static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
> uint32_t offset;
>
> /* cache window 0: fw */
> @@ -412,7 +412,7 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
>
> static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
> uint32_t offset;
>
> /* cache window 0: fw */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index de4067713d7b..e42cfc731ad8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -372,7 +372,7 @@ static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
> */
> static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
> uint32_t offset;
>
> if (amdgpu_sriov_vf(adev))
> @@ -428,7 +428,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
>
> static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
> uint32_t offset;
>
> /* cache window 0: fw */
> @@ -1920,7 +1920,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
>
> init_table += header->vcn_table_offset;
>
> - size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
> + size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
>
> MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
> SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 08f43a281a7f..b518202955ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -465,7 +465,7 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
> if (adev->vcn.harvest_config & (1 << i))
> continue;
>
> - size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
> + size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
> /* cache window 0: fw */
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> @@ -514,7 +514,7 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
>
> static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);
> uint32_t offset;
>
> /* cache window 0: fw */
> @@ -1287,7 +1287,7 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
> SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
> ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
>
> - size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
> + size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
> /* mc resume*/
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> MMSCH_V1_0_INSERT_DIRECT_WT(
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 6002990d917b..63ddd4cca910 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -490,7 +490,7 @@ static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block)
> */
> static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4);
> uint32_t offset;
>
> /* cache window 0: fw */
> @@ -540,7 +540,7 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
>
> static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
> {
> - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4);
> + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);
> uint32_t offset;
>
> /* cache window 0: fw */
> @@ -1375,7 +1375,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
> mmUVD_STATUS),
> ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
>
> - cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
> + cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 2c36f748176f..1a6257d324c9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -422,7 +422,7 @@ static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> @@ -482,7 +482,7 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> {
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> @@ -1334,7 +1334,7 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
> regUVD_STATUS),
> ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
>
> - cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
> + cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index eda67585768f..23a2a80129bb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -377,7 +377,7 @@ static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)
> uint32_t offset, size, vcn_inst;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> vcn_inst = GET_INST(VCN, inst_idx);
> @@ -452,7 +452,7 @@ static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> @@ -939,7 +939,7 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
> MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
> ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
>
> - cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
> + cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index f24e1eef6606..e49ba5bc7fa0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -370,7 +370,7 @@ static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> @@ -431,7 +431,7 @@ static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 8ccd054975a1..900ca8ababc1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -334,7 +334,7 @@ static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst)
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> @@ -395,7 +395,7 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> - hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
> + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
> size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>
> /* cache window 0: fw */
> --
> 2.34.1
>
