[AMD Official Use Only - AMD Internal Distribution Only]
> -----Original Message-----
> From: Sharma, Shashank <Shashank.Sharma@xxxxxxx>
> Sent: Thursday, October 10, 2024 2:08 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Somalapuram, Amaranath <Amaranath.Somalapuram@xxxxxxx>; Deucher,
> Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian
> <Christian.Koenig@xxxxxxx>; Yadav, Arvind <Arvind.Yadav@xxxxxxx>; Sharma,
> Shashank <Shashank.Sharma@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: enable userqueue support for GFX12
>
> From: Somalapuram Amaranath <Amaranath.Somalapuram@xxxxxxx>
>
> This patch enables Usermode queue support across GFX, Compute and SDMA IPs
> on GFX12/SDMA7. It typically reuses Navi3X userqueue IP functions to create and
> destroy MQDs.
I would like to make this more explicit. In mes_v11_0_userqueue.c, I would suggest splitting out any non-gfx11 specific code into some new helpers in mes_userqueue.c. E.g.,
mes_v11_0_map_gtt_bo_to_gart() -> mes_userq_map_gtt_bo_to_gart()
mes_v11_0_create_wptr_mapping() -> mes_userq_create_wptr_mapping()
mes_v11_0_userq_map() -> mes_userq_map()
mes_v11_0_userq_unmap() -> mes_userq_unmap()
mes_v11_0_userq_mqd_destroy() -> mes_userq_mqd_destroy()
However, mes_v11_userq_create_ctx_space() uses the v11 mqd structures which may not match the v12 structures. We should add a v12 implementation for any functions that use the v12 structures.
Alex
>
> Cc: Alex Deucher <alexander.deucher@xxxxxxx>
> Cc: Christian Koenig <christian.koenig@xxxxxxx>
> Cc: Arvind Yadav <arvind.yadav@xxxxxxx>
> Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@xxxxxxx>
> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 5 +++++
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 6 ++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 9fec28d8a5fc..d511996c374d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -46,6 +46,7 @@
> #include "gfx_v12_0.h"
> #include "nbif_v6_3_1.h"
> #include "mes_v12_0.h"
> +#include "mes_v11_0_userqueue.h"
>
> #define GFX12_NUM_GFX_RINGS 1
> #define GFX12_MEC_HPD_SIZE 2048
> @@ -1335,6 +1336,10 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block
> *ip_block)
> adev->gfx.mec.num_mec = 2;
> adev->gfx.mec.num_pipe_per_mec = 2;
> adev->gfx.mec.num_queue_per_pipe = 4;
> +#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
> + adev->userq_funcs[AMDGPU_HW_IP_GFX] =
> &userq_mes_v11_0_funcs;
> + adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] =
> &userq_mes_v11_0_funcs;
> +#endif
> break;
> default:
> adev->gfx.me.num_me = 1;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 24f24974ac1d..badcf38bb8b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -42,6 +42,7 @@
> #include "sdma_common.h"
> #include "sdma_v7_0.h"
> #include "v12_structs.h"
> +#include "mes_v11_0_userqueue.h"
>
> MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin");
> MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin");
> @@ -1317,6 +1318,11 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block
> *ip_block)
> else
> DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
>
> +#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
> + adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_v11_0_funcs;
> #endif
> +
> +
> return r;
> }
>
> --
> 2.46.2
