> -----Original Message----- > From: Liu, Monk > Sent: Tuesday, May 02, 2017 4:32 AM > To: Alex Deucher; amd-gfx at lists.freedesktop.org > Cc: Deucher, Alexander > Subject: RE: [PATCH 07/12] drm/amdgpu/gfx9: wait for completion in KIQ init > > Reviewed-by: monk liu <monk.liu at amd.com> > > But why we need to do this ? even kiq hasn't yet finished MAP_QUEUES, we > can still put ring test package to KCQ, > And KCQ will begin to work after the MAP_QUEUES finished .... I was concerned the doorbell to kick off the ring test, etc. would get silently ignored if the KCQ had not yet been initialized by the KIQ. Alex > > BR Monk > > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Alex Deucher > Sent: Tuesday, May 02, 2017 6:29 AM > To: amd-gfx at lists.freedesktop.org > Cc: Deucher, Alexander <Alexander.Deucher at amd.com> > Subject: [PATCH 07/12] drm/amdgpu/gfx9: wait for completion in KIQ init > > We need to make sure the various init sequences submitted to KIQ complete > before testing the rings. > > Signed-off-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 89 > +++++++++++++++++++++++++++++++---- > 1 file changed, 79 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index d9b9fb8..ca30726 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1811,9 +1811,26 @@ static void gfx_v9_0_kiq_setting(struct > amdgpu_ring *ring) > WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); } > > -static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) > +static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) > { > - amdgpu_ring_alloc(ring, 8); > + struct amdgpu_device *adev = ring->adev; > + uint32_t scratch, tmp = 0; > + int r, i; > + > + r = amdgpu_gfx_scratch_get(adev, &scratch); > + if (r) { > + DRM_ERROR("Failed to get scratch reg (%d).\n", r); > + return r; > + } > + WREG32(scratch, 0xCAFEDEAD); > + > + r = amdgpu_ring_alloc(ring, 8); > + if (r) { > + DRM_ERROR("Failed to lock KIQ (%d).\n", r); > + amdgpu_gfx_scratch_free(adev, scratch); > + return r; > + } > + amdgpu_ring_alloc(ring, 11); > /* set resources */ > amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); > amdgpu_ring_write(ring, > PACKET3_SET_RESOURCES_VMID_MASK(0) | @@ -1824,19 +1841,52 @@ > static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) > amdgpu_ring_write(ring, 0); /* gws mask hi */ > amdgpu_ring_write(ring, 0); /* oac mask */ > amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 > */ > + /* write to scratch for completion */ > + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, > 1)); > + amdgpu_ring_write(ring, (scratch - > PACKET3_SET_UCONFIG_REG_START)); > + amdgpu_ring_write(ring, 0xDEADBEEF); > amdgpu_ring_commit(ring); > - udelay(50); > + > + for (i = 0; i < adev->usec_timeout; i++) { > + tmp = RREG32(scratch); > + if (tmp == 0xDEADBEEF) > + break; > + DRM_UDELAY(1); > + } > + if (i >= adev->usec_timeout) { > + DRM_ERROR("KIQ enable failed > (scratch(0x%04X)=0x%08X)\n", > + scratch, tmp); > + r = -EINVAL; > + } > + amdgpu_gfx_scratch_free(adev, scratch); > + > + return r; > } > > -static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, > - struct amdgpu_ring *ring) > +static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, > + struct amdgpu_ring *ring) > { > struct amdgpu_device *adev = kiq_ring->adev; > uint64_t mqd_addr, wptr_addr; > + uint32_t scratch, tmp = 0; > + int r, i; > + > + r = amdgpu_gfx_scratch_get(adev, &scratch); > + if (r) { > + DRM_ERROR("Failed to get scratch reg (%d).\n", r); > + return r; > + } > + WREG32(scratch, 0xCAFEDEAD); > + > + r = amdgpu_ring_alloc(kiq_ring, 10); > + if (r) { > + DRM_ERROR("Failed to lock KIQ (%d).\n", r); > + amdgpu_gfx_scratch_free(adev, scratch); > + return r; > + } > > mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); > wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); > - amdgpu_ring_alloc(kiq_ring, 8); > > amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); > /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ @@ -1855,8 > +1905,26 @@ static void gfx_v9_0_map_queue_enable(struct amdgpu_ring > *kiq_ring, > amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); > amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); > amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); > + /* write to scratch for completion */ > + amdgpu_ring_write(kiq_ring, > PACKET3(PACKET3_SET_UCONFIG_REG, 1)); > + amdgpu_ring_write(kiq_ring, (scratch - > PACKET3_SET_UCONFIG_REG_START)); > + amdgpu_ring_write(kiq_ring, 0xDEADBEEF); > amdgpu_ring_commit(kiq_ring); > - udelay(50); > + > + for (i = 0; i < adev->usec_timeout; i++) { > + tmp = RREG32(scratch); > + if (tmp == 0xDEADBEEF) > + break; > + DRM_UDELAY(1); > + } > + if (i >= adev->usec_timeout) { > + DRM_ERROR("KCQ enable failed > (scratch(0x%04X)=0x%08X)\n", > + scratch, tmp); > + r = -EINVAL; > + } > + amdgpu_gfx_scratch_free(adev, scratch); > + > + return r; > } > > static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) @@ -2102,6 +2170,7 > @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) > struct v9_mqd *mqd = ring->mqd_ptr; > bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); > int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; > + int r; > > if (is_kiq) { > gfx_v9_0_kiq_setting(&kiq->ring); > @@ -2140,11 +2209,11 @@ static int gfx_v9_0_kiq_init_queue(struct > amdgpu_ring *ring) > } > > if (is_kiq) > - gfx_v9_0_kiq_enable(ring); > + r = gfx_v9_0_kiq_enable(ring); > else > - gfx_v9_0_map_queue_enable(&kiq->ring, ring); > + r = gfx_v9_0_map_queue_enable(&kiq->ring, ring); > > - return 0; > + return r; > } > > static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) > -- > 2.5.5 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
