On Tue, Oct 8, 2024 at 11:30 AM Shashank Sharma <shashank.sharma@xxxxxxx> wrote:
>
> Currently, the shadow FW space size and alignment information is
> protected under a flag (adev->gfx.cp_gfx_shadow) which gets set
> only in case of SRIOV setups.
> if (amdgpu_sriov_vf(adev))
> adev->gfx.cp_gfx_shadow = true;
>
> But we need this information for GFX Userqueues, so that user can
> create these objects while creating userqueue. This patch series
> creates a method to get this information bypassing the dependency
> on this check.
>
> This patch:
> - adds a new subquery (AMDGPU_INFO_FW_OBJ_SZ) in
> AMDGPU_INFO_IOCTL to get the size and alignment of shadow
> and csa objects from the FW setup.
> - adds a new input parameter flag to the gfx.funcs->get_gfx_shadow_info
> fptr definition, so that it can accommodate the information without the
> check (adev->gfx.cp_gfx_shadow) on request.
> - updates the existing definition of amdgpu_gfx_get_gfx_shadow_info to
> adjust with this new flag.
>
> Cc: Alex Deucher <alexander.deucher@xxxxxxx>
> Cc: Christian Koenig <christian.koenig@xxxxxxx>
> Cc: Arvind Yadav <arvind.yadav@xxxxxxx>
> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 5 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 19 +++++++++++++------
> include/uapi/drm/amdgpu_drm.h | 2 ++
> 4 files changed, 32 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index f710178a21bc..efea172c41b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -302,7 +302,8 @@ struct amdgpu_gfx_funcs {
> void (*init_spm_golden)(struct amdgpu_device *adev);
> void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
> int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
> - struct amdgpu_gfx_shadow_info *shadow_info);
> + struct amdgpu_gfx_shadow_info *shadow_info,
> + bool skip_check);
> enum amdgpu_gfx_partition
> (*query_partition_mode)(struct amdgpu_device *adev);
> int (*switch_partition_mode)(struct amdgpu_device *adev,
> @@ -491,7 +492,7 @@ struct amdgpu_gfx_ras_mem_id_entry {
> #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
> #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))
> #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
> -#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
> +#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false))
>
> /**
> * amdgpu_gfx_create_bitmask - create a bitmask
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index b53c35992152..8521b62cc136 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -1282,6 +1282,20 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
> return copy_to_user(out, &gpuvm_fault,
> min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
> }
> + case AMDGPU_INFO_FW_OBJ_SZ: {
> + struct amdgpu_gfx_shadow_info shadow_info;
> +
> + memset(&shadow_info, 0, sizeof(shadow_info));
> + if (adev->gfx.funcs->get_gfx_shadow_info) {
> + adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true);
> + ret = copy_to_user(out, &shadow_info,
> + min((size_t)size, sizeof(shadow_info))) ? -EFAULT : 0;
> + } else {
> + ret = -EOPNOTSUPP;
> + }
> +
> + return ret;
> + }
> default:
> DRM_DEBUG_KMS("Invalid request %d\n", info->query);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 1d5c873876f5..e5f5de8804b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -1034,14 +1034,21 @@ static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
> #define MQD_FWWORKAREA_SIZE 484
> #define MQD_FWWORKAREA_ALIGNMENT 256
>
> -static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
> +static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,
> struct amdgpu_gfx_shadow_info *shadow_info)
> {
> - if (adev->gfx.cp_gfx_shadow) {
> - shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
> - shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
> - shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
> - shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
> + shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
> + shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
> + shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
> + shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
> +}
> +
> +static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
> + struct amdgpu_gfx_shadow_info *shadow_info,
> + bool skip_check)
> +{
> + if (adev->gfx.cp_gfx_shadow || skip_check) {
> + gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info);
> return 0;
> } else {
> memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index d9bff1c3b326..ad35b41be250 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -1052,6 +1052,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
> #define AMDGPU_INFO_MAX_IBS 0x22
> /* query last page fault info */
> #define AMDGPU_INFO_GPUVM_FAULT 0x23
> +/* query FW object size and alignment */
> +#define AMDGPU_INFO_FW_OBJ_SZ 0x24
Maybe something like:
AMDGPU_INFO_UQ_METADATA to make it clearer what it's for. Also I
think we want to make the input the IP type so we can extend this to
other IPs in the future if necessary. We should also be explicit with
the output format so it's clear to userspace how to use the query.
Something like the attached patch.
Alex
>
> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> --
> 2.46.0
>
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index efe5de6ce208..f62be6f380ce 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -923,6 +923,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_INFO_MAX_IBS 0x22
/* query last page fault info */
#define AMDGPU_INFO_GPUVM_FAULT 0x23
+/* query user queue metadata */
+#define AMDGPU_INFO_GPUVM_FAULT 0x24
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -994,6 +996,11 @@ struct drm_amdgpu_info {
struct {
__u32 type;
} video_cap;
+
+ struct {
+ /** AMDGPU_HW_IP_* */
+ __u32 type;
+ } uq_metadata;
};
};
@@ -1262,6 +1269,23 @@ struct drm_amdgpu_info_gpuvm_fault {
__u32 vmhub;
};
+struct drm_amdgpu_info_uq_metadata_gfx {
+ /* shadow area size for gfx11 */
+ __u32 shadow_size;
+ /* shadow area base virtual alignment for gfx11 */
+ __u32 shadow_alignment;
+ /* context save area size for gfx11 */
+ __u32 csa_size;
+ /* context save area base virtual alignment for gfx11 */
+ __u32 csa_alignment;
+};
+
+struct drm_amdgpu_info_uq_metadata {
+ union {
+ struct drm_amdgpu_info_uq_metadata_gfx gfx;
+ };
+};
+
/*
* Supported GPU families
*/
