From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxx>
Similar to the previous patch but with the addition of a magic bit1 set on
big endian platforms. No idea what it is but maybe adding a helper and
giving both it and the magic bit a proper name would be worth it.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxx>
Cc: Christian König <ckoenig.leichtzumerken@xxxxxxxxx>
Cc: Sunil Khatri <sunil.khatri@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 13 +++++++++++++
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++------------
2 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index aeab6fe21db6..68f3799f173c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -503,6 +503,19 @@ static inline void amdgpu_ring_write_addr(struct amdgpu_ring *ring, u64 addr)
amdgpu_ring_write64(ring, v);
}
+static inline void
+amdgpu_ring_write_addr_xbe(struct amdgpu_ring *ring, u64 addr)
+{
+ u64 v;
+
+#ifdef __BIG_ENDIAN
+ v = (u64)lower_32_bits(addr) << 32 | upper_32_bits(addr) | (2 << 0); /* Magic bit name? */
+#else
+ v = addr;
+#endif
+ amdgpu_ring_write64(ring, v);
+}
+
/**
* amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
* @ring: amdgpu_ring structure
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 24fb58543041..de1909c1de49 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8549,12 +8549,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, header);
BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
- amdgpu_ring_write(ring,
-#ifdef __BIG_ENDIAN
- (2 << 0) |
-#endif
- lower_32_bits(ib->gpu_addr));
- amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write_addr_xbe(ring, ib->gpu_addr);
amdgpu_ring_write(ring, control);
}
@@ -8584,12 +8579,7 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
- amdgpu_ring_write(ring,
-#ifdef __BIG_ENDIAN
- (2 << 0) |
-#endif
- lower_32_bits(ib->gpu_addr));
- amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write_addr_xbe(ring, ib->gpu_addr);
amdgpu_ring_write(ring, control);
}
--
2.46.0
