[PATCH 1/2] drm/amdgpu/mes11: update mes_reset_queue function to support sdma queue

[<jiadong.zhu@xxxxxxx>]

From: Jiadong Zhu <Jiadong.Zhu@xxxxxxx>

Reset sdma queue through mmio based on me_id and queue_id.

Signed-off-by: Jiadong Zhu <Jiadong.Zhu@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 53 ++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 5174ed31ae5c..285ea4cdd5b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -914,7 +914,7 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
 	queue_input.me_id = ring->me;
 	queue_input.pipe_id = ring->pipe;
 	queue_input.queue_id = ring->queue;
-	queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+	queue_input.mqd_addr = ring->mqd_obj ? amdgpu_bo_gpu_offset(ring->mqd_obj) : 0;
 	queue_input.wptr_addr = ring->wptr_gpu_addr;
 	queue_input.vmid = vmid;
 	queue_input.use_mmio = use_mmio;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c4212b6fbc56..2b94a8e7f509 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -366,7 +366,7 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ
 				      uint32_t queue_id, uint32_t vmid)
 {
 	struct amdgpu_device *adev = mes->adev;
-	uint32_t value;
+	uint32_t value, reg;
 	int i, r = 0;
 
 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
@@ -422,6 +422,57 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ
 		}
 		soc21_grbm_select(adev, 0, 0, 0, 0);
 		mutex_unlock(&adev->srbm_mutex);
+	} else if (queue_type == AMDGPU_RING_TYPE_SDMA) {
+		switch (me_id) {
+		case 0:
+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
+			break;
+		case 1:
+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
+			break;
+		default:
+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
+		}
+
+		switch (queue_id) {
+		case 0:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT;
+			break;
+		case 1:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT;
+			break;
+		case 2:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT;
+			break;
+		case 3:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT;
+			break;
+		case 4:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT;
+			break;
+		case 5:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT;
+			break;
+		case 6:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT;
+			break;
+		case 7:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT;
+			break;
+		default:
+			value = 1 << SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT;
+		}
+		WREG32(reg, value);
+		/* wait for queue reset done */
+		for (i = 0; i < adev->usec_timeout; i++) {
+			if (!(RREG32(reg) & value))
+				break;
+			udelay(1);
+		}
+		if (i >= adev->usec_timeout) {
+			dev_err(adev->dev, "failed to wait on sdma queue reset done\n");
+			r = -ETIMEDOUT;
+		}
 	}
 
 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
-- 
2.25.1