[PATCH 1/2] drm/amdgpu/psp: add check sOS sign

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> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
> Of Xiangliang Yu
> Sent: Wednesday, March 29, 2017 5:27 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Yu, Xiangliang
> Subject: [PATCH 1/2] drm/amdgpu/psp: add check sOS sign
> 
> Confirm if sys driver and sOS are already been loaded through sOS
> sign register, skip loading sys driver and sOS if finding the sign.
> 
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu at amd.com>

Series is:
Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 49c3844..5191c45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -170,7 +170,14 @@ int psp_v3_1_bootloader_load_sysdrv(struct
> psp_context *psp)
>  	void *psp_sysdrv_virt = NULL;
>  	uint64_t psp_sysdrv_mem;
>  	struct amdgpu_device *adev = psp->adev;
> -	uint32_t size;
> +	uint32_t size, sol_reg;
> +
> +	/* Check sOS sign of life register to confirm sys driver and sOS
> +	 * are already been loaded.
> +	 */
> +	sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_C2PMSG_81));
> +	if (sol_reg)
> +		return 0;
> 
>  	/* Wait for bootloader to signify that is ready having bit 31 of
> C2PMSG_35 set to 1 */
>  	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_C2PMSG_35),
> @@ -222,7 +229,14 @@ int psp_v3_1_bootloader_load_sos(struct
> psp_context *psp)
>  	void *psp_sos_virt = NULL;
>  	uint64_t psp_sos_mem;
>  	struct amdgpu_device *adev = psp->adev;
> -	uint32_t size;
> +	uint32_t size, sol_reg;
> +
> +	/* Check sOS sign of life register to confirm sys driver and sOS
> +	 * are already been loaded.
> +	 */
> +	sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_C2PMSG_81));
> +	if (sol_reg)
> +		return 0;
> 
>  	/* Wait for bootloader to signify that is ready having bit 31 of
> C2PMSG_35 set to 1 */
>  	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_C2PMSG_35),
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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