> > +
> > + reset_pipe = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
> regCP_MEC_CNTL);
> > + clean_pipe = reset_pipe;
>
> I think the saved value could be written back (skipping the SET_FIELD steps
> below) as the only change that's done here is to set the PIPEx_RESET field.
>
Yes, it seems that using the variable clean_pipe to save the original value will be okay for cleaning up
the pipe reset field, as there is a mutex lock to ensure that the pipe reset field is mutually set.
It can simplify the code, but it does not appear to be straightforward to set and clean the pipe reset field.
Thanks,
Prike
> Apart from those, looks fine.
>
> Thanks,
> Lijo
>
> > +
> > + if (me == 1) {
> > + switch (pipe) {
> > + case 0:
> > + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE0_RESET, 1);
> > + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE0_RESET, 0);
> > + break;
> > + case 1:
> > + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE1_RESET, 1);
> > + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE1_RESET, 0);
> > + break;
> > + case 2:
> > + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE2_RESET, 1);
> > + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE2_RESET, 0);
> > + break;
> > + case 3:
> > + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE3_RESET, 1);
> > + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> > + MEC_ME1_PIPE3_RESET, 0);
> > + break;
> > + default:
> > + break;
> > + }
> > + } else {
> > + if (pipe) {
> > + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_CNTL,
> > + MEC_ME2_PIPE1_RESET, 1);
> > + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> > + MEC_ME2_PIPE1_RESET, 0);
> > + } else {
> > + reset_pipe = REG_SET_FIELD(reset_pipe,
> CP_MEC_CNTL,
> > + MEC_ME2_PIPE0_RESET, 1);
> > + clean_pipe = REG_SET_FIELD(clean_pipe,
> CP_MEC_CNTL,
> > + MEC_ME2_PIPE0_RESET, 0);
> > + }
> > + }
> > +
> > + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
> reset_pipe);
> > + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
> clean_pipe);
> > + soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
> > + mutex_unlock(&adev->srbm_mutex);
> > + gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id);
> > +
> > + r = gfx_v9_4_3_unmap_done(adev, me, pipe, queue, xcc_id);
> > + return r;
> > +}
> > +
> > static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
> > unsigned int vmid)
> > {
> > @@ -3473,7 +3588,7 @@ static int gfx_v9_4_3_reset_kcq(struct
> amdgpu_ring *ring,
> > struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id];
> > struct amdgpu_ring *kiq_ring = &kiq->ring;
> > unsigned long flags;
> > - int r, i;
> > + int r;
> >
> > if (amdgpu_sriov_vf(adev))
> > return -EINVAL;
> > @@ -3495,26 +3610,25 @@ static int gfx_v9_4_3_reset_kcq(struct
> amdgpu_ring *ring,
> > spin_unlock_irqrestore(&kiq->ring_lock, flags);
> >
> > r = amdgpu_ring_test_ring(kiq_ring);
> > - if (r)
> > - return r;
> > -
> > - /* make sure dequeue is complete*/
> > - amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id);
> > - mutex_lock(&adev->srbm_mutex);
> > - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0,
> GET_INST(GC, ring->xcc_id));
> > - for (i = 0; i < adev->usec_timeout; i++) {
> > - if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
> > - break;
> > - udelay(1);
> > - }
> > - if (i >= adev->usec_timeout)
> > - r = -ETIMEDOUT;
> > - soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, ring->xcc_id));
> > - mutex_unlock(&adev->srbm_mutex);
> > - amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id);
> > if (r) {
> > - dev_err(adev->dev, "fail to wait on hqd deactive\n");
> > - return r;
> > + dev_err(adev->dev, "kiq ring test failed after ring: %s queue
> reset\n",
> > + ring->name);
> > + goto pipe_reset;
> > + }
> > +
> > + r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring-
> >queue, ring->xcc_id);
> > + if (r)
> > + dev_err(adev->dev, "fail to wait on hqd deactive and will try
> pipe
> > +reset\n");
> > +
> > +pipe_reset:
> > + if(r) {
> > + r = gfx_v9_4_3_kiq_reset_hw_pipe(kiq_ring, ring->funcs-
> >type,
> > + ring->me, ring->pipe,
> > + ring->queue, ring->xcc_id);
> > + dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name,
> > + r ? "failed" : "successfully");
> > + if (r)
> > + return r;
> > }
> >
> > r = amdgpu_bo_reserve(ring->mqd_obj, false);
