[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Emily Deng <Emily.Deng@xxxxxxx>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Victor
>Zhao
>Sent: Monday, August 19, 2024 11:50 AM
>To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: Deng, Emily <Emily.Deng@xxxxxxx>; Zhao, Victor
><Victor.Zhao@xxxxxxx>
>Subject: [PATCH] drm/amd/amdgpu: allow use kiq to do hdp flush under sriov
>
>when use cpu to do page table update under sriov runtime, since mmio
>access is blocked, kiq has to be used to flush hdp.
>
>change WREG32_NO_KIQ to WREG32 to allow kiq.
>
>Signed-off-by: Victor Zhao <Victor.Zhao@xxxxxxx>
>---
> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 2 +-
>drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c | 2 +-
>drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c | 2 +-
>drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>index 077c6d920e27..e019249883fb 100644
>--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>@@ -41,7 +41,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device
>*adev,
> struct amdgpu_ring *ring)
> {
> if (!ring || !ring->funcs->emit_wreg)
>- WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
>KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>+ WREG32((adev->rmmio_remap.reg_offset +
>+KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> else
> amdgpu_ring_emit_wreg(ring, (adev-
>>rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
>2, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
>b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
>index a9ea23fa0def..ed7facacf2fe 100644
>--- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
>@@ -32,7 +32,7 @@ static void hdp_v5_0_flush_hdp(struct amdgpu_device
>*adev,
> struct amdgpu_ring *ring)
> {
> if (!ring || !ring->funcs->emit_wreg)
>- WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
>KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>+ WREG32((adev->rmmio_remap.reg_offset +
>+KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> else
> amdgpu_ring_emit_wreg(ring, (adev-
>>rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
>2, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
>b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
>index ab06c2b4b20b..33736d361dd0 100644
>--- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
>@@ -35,7 +35,7 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device
>*adev,
> struct amdgpu_ring *ring)
> {
> if (!ring || !ring->funcs->emit_wreg)
>- WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
>KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>+ WREG32((adev->rmmio_remap.reg_offset +
>+KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> else
> amdgpu_ring_emit_wreg(ring, (adev-
>>rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
>2, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
>b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
>index 8d7d0813e331..1c99bb09e2a1 100644
>--- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c
>@@ -32,7 +32,7 @@ static void hdp_v7_0_flush_hdp(struct amdgpu_device
>*adev,
> struct amdgpu_ring *ring)
> {
> if (!ring || !ring->funcs->emit_wreg)
>- WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
>KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
>+ WREG32((adev->rmmio_remap.reg_offset +
>+KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
> else
> amdgpu_ring_emit_wreg(ring, (adev-
>>rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
>2, 0); }
>--
>2.34.1
