From: Roman Li <Roman.Li@xxxxxxx>
In some use-cases, e.g. multiple 4K displays,
exisitng wait time for reg update of 30msec timed out
during mode setiing that sometimes resulted in system bad state
as we continue without waiting for registry update complete.
Increasing timeout to 35msec fixes that problem.
Change-Id: I280155f6e336066b810fe9e3533c345114aca725
Signed-off-by: Roman Li <Roman.Li at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 7acd87152811..884f453d91b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -524,7 +524,7 @@ void dce_mem_input_free_dmif(struct mem_input *mi,
REG_WAIT(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
- 10, 0xBB8);
+ 10, 3500);
if (mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
--
2.11.0
