[PATCH 5/6] drm/amdgpu: Implement disabling implicit sync per submission.

[Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx>]

Signed-off-by: Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 ++++++++++++++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h |  1 +
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8d6f42e308fb..e1ba48644a0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -185,9 +185,11 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
 	int ret;
 	int i;
 
-	if (cs->in.flags)
+	if (cs->in.flags & ~AMDGPU_CS_FLAGS_MASK)
 		return -EINVAL;
 
+	p->flags = cs->in.flags;
+
 	chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
 				     GFP_KERNEL);
 	if (!chunk_array)
@@ -1194,15 +1196,18 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 	}
 
 	drm_exec_for_each_locked_object(&p->exec, index, obj) {
+		enum dma_resv_usage usage = DMA_RESV_USAGE_READ;
 		struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 
 		struct dma_resv *resv = bo->tbo.base.resv;
 		enum amdgpu_sync_mode sync_mode;
 
+		if (p->flags & AMDGPU_CS_NO_IMPLICIT_SYNC)
+			usage = DMA_RESV_USAGE_KERNEL;
+
 		sync_mode = amdgpu_bo_explicit_sync(bo) ?
 			AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
-		r = amdgpu_sync_resv(p->adev, &p->sync, resv,
-				     DMA_RESV_USAGE_READ, sync_mode,
+		r = amdgpu_sync_resv(p->adev, &p->sync, resv, usage, sync_mode,
 				     &fpriv->vm);
 		if (r)
 			return r;
@@ -1259,6 +1264,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 {
 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 	struct amdgpu_job *leader = p->gang_leader;
+	enum dma_resv_usage read_usage = DMA_RESV_USAGE_READ;
+	enum dma_resv_usage write_usage = DMA_RESV_USAGE_WRITE;
 	struct amdgpu_bo_list_entry *e;
 	struct drm_gem_object *gobj;
 	unsigned long index;
@@ -1310,6 +1317,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 		return r;
 	}
 
+	if (p->flags & AMDGPU_CS_NO_IMPLICIT_SYNC) {
+		read_usage = write_usage = DMA_RESV_USAGE_BOOKKEEP;
+	}
+
 	p->fence = dma_fence_get(&leader->base.s_fence->finished);
 	drm_exec_for_each_locked_object(&p->exec, index, gobj) {
 
@@ -1322,11 +1333,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 
 			dma_resv_add_fence(gobj->resv,
 					   &p->jobs[i]->base.s_fence->finished,
-					   DMA_RESV_USAGE_READ);
+					   read_usage);
 		}
 
 		/* The gang leader as remembered as writer */
-		dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE);
+		dma_resv_add_fence(gobj->resv, p->fence, write_usage);
 	}
 
 	seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h
index 39c33ad100cb..683c6eca4f1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h
@@ -50,6 +50,7 @@ struct amdgpu_cs_parser {
 	struct amdgpu_device	*adev;
 	struct drm_file		*filp;
 	struct amdgpu_ctx	*ctx;
+	uint32_t		flags;
 
 	/* chunks */
 	unsigned		nchunks;
-- 
2.45.2