This partially reverts commit b7a1a0ef12b81957584fef7b61e2d5ec049c7209. A user reported stuttering under heavy gfx load with this commit. I suspect it's due to the fact that the gfx contexts are shared between the pipes so if there is alot of load on one pipe, we could end up stalling waiting for a context. That said, having both pipes is useful in some contexts and this patch was actually enabled mainly to support some SR-IOV use cases, so leave it enabled for SR-IOV. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3519 Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> Cc: ZhenGuo Yin <zhenguo.yin@xxxxxxx> Cc: Alex Deucher <alexander.deucher@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 1b88528b512b..f25389e2ec3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4710,7 +4710,10 @@ static int gfx_v10_0_sw_init(void *handle) case IP_VERSION(10, 3, 3): case IP_VERSION(10, 3, 7): adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 2; + if (amdgpu_sriov_vf(adev)) + adev->gfx.me.num_pipe_per_me = 2; + else + adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; -- 2.45.2
