On 17-03-25 10:00 AM, Christian König wrote:
> Sorry, I wasn't clear about this. GB_ADDR_CONFIG is still needed even
> in Vega10.
>
> But CC_RB_BACKEND_DISABLE and GC_USER_RB_BACKEND_DISABLE aren't used
> any more as far as I can see.
>
> The mask resulting from those two registers is computed during GFX9
> startup, cached and given to user mode in enabled_rb_pipes_mask.
Sounds good. KFD doesn't expose MMIO register directly to user mode. We
return the cached gb_addr_config, enabled CUs in adev->gfx.cu_info, and
tiling mode arrays in adev->gfx.config, but we don't use any information
about RBs.
Regards,
Felix
>
> I think we should disallow reading CC_RB_BACKEND_DISABLE and
> GC_USER_RB_BACKEND_DISABLE through this interface.
>
> Regards,
> Christian.
>
> Am 24.03.2017 um 21:08 schrieb Felix Kuehling:
>> We're reporting gb_addr_config to user mode in our KFD tiling info API.
>>
>> If this is no longer needed by user mode for soc15, we could just put in
>> a dummy value. However, I haven't been told that it can be removed for
>> older ASICs.
>>
>> Regards,
>> Felix
>>
>>
>> On 17-03-24 03:48 PM, Alex Deucher wrote:
>>> On Fri, Mar 24, 2017 at 3:44 PM, Christian König
>>> <deathsimple at vodafone.de> wrote:
>>>> Am 24.03.2017 um 20:13 schrieb Alex Deucher:
>>>>> Required for SR-IOV and saves MMIO transactions.
>>>>>
>>>>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>>>> As far as I can see they are not used any more by userspace and the
>>>> same
>>>> info is available in enabled_rb_pipes_mask.
>>>>
>>>> So why do you want to keep them?
>>> Does anything use mmGB_ADDR_CONFIG? If not, I agree, we can drop the
>>> whole thing. Not sure if any of the closed UMDs use them or not off
>>> hand.
>>>
>>> Alex
>>>
>>>> Regards,
>>>> Christian.
>>>>
>>>>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 40
>>>>> ++++++++++++++++++++++++++++++--------
>>>>> 1 file changed, 32 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>>>>> index 804bd8d..441e0f4 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>>>>> @@ -322,6 +322,32 @@ static uint32_t
>>>>> soc15_read_indexed_register(struct
>>>>> amdgpu_device *adev, u32 se_n
>>>>> return val;
>>>>> }
>>>>> +static uint32_t soc15_get_register_value(struct amdgpu_device
>>>>> *adev,
>>>>> + bool indexed, u32 se_num,
>>>>> + u32 sh_num, u32 reg_offset)
>>>>> +{
>>>>> + if (indexed) {
>>>>> + unsigned se_idx = (se_num == 0xffffffff) ? 0 :
>>>>> se_num;
>>>>> + unsigned sh_idx = (sh_num == 0xffffffff) ? 0 :
>>>>> sh_num;
>>>>> +
>>>>> + switch (reg_offset) {
>>>>> + case SOC15_REG_OFFSET(GC, 0,
>>>>> mmCC_RB_BACKEND_DISABLE):
>>>>> + return
>>>>> adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
>>>>> + case SOC15_REG_OFFSET(GC, 0,
>>>>> mmGC_USER_RB_BACKEND_DISABLE):
>>>>> + return
>>>>> adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
>>>>> + }
>>>>> +
>>>>> + return soc15_read_indexed_register(adev, se_num,
>>>>> sh_num,
>>>>> reg_offset);
>>>>> + } else {
>>>>> + switch (reg_offset) {
>>>>> + case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
>>>>> + return adev->gfx.config.gb_addr_config;
>>>>> + default:
>>>>> + return RREG32(reg_offset);
>>>>> + }
>>>>> + }
>>>>> +}
>>>>> +
>>>>> static int soc15_read_register(struct amdgpu_device *adev, u32
>>>>> se_num,
>>>>> u32 sh_num, u32 reg_offset, u32 *value)
>>>>> {
>>>>> @@ -345,10 +371,9 @@ static int soc15_read_register(struct
>>>>> amdgpu_device
>>>>> *adev, u32 se_num,
>>>>> if (reg_offset !=
>>>>> asic_register_entry->reg_offset)
>>>>> continue;
>>>>> if (!asic_register_entry->untouched)
>>>>> - *value =
>>>>> asic_register_entry->grbm_indexed
>>>>> ?
>>>>> -
>>>>> soc15_read_indexed_register(adev,
>>>>> se_num,
>>>>> -
>>>>> sh_num,
>>>>> reg_offset) :
>>>>> - RREG32(reg_offset);
>>>>> + *value =
>>>>> soc15_get_register_value(adev,
>>>>> +
>>>>> asic_register_entry->grbm_indexed,
>>>>> +
>>>>> se_num,
>>>>> sh_num, reg_offset);
>>>>> return 0;
>>>>> }
>>>>> }
>>>>> @@ -358,10 +383,9 @@ static int soc15_read_register(struct
>>>>> amdgpu_device
>>>>> *adev, u32 se_num,
>>>>> continue;
>>>>> if (!soc15_allowed_read_registers[i].untouched)
>>>>> - *value =
>>>>> soc15_allowed_read_registers[i].grbm_indexed ?
>>>>> - soc15_read_indexed_register(adev,
>>>>> se_num,
>>>>> - sh_num,
>>>>> reg_offset) :
>>>>> - RREG32(reg_offset);
>>>>> + *value = soc15_get_register_value(adev,
>>>>> +
>>>>> soc15_allowed_read_registers[i].grbm_indexed,
>>>>> + se_num,
>>>>> sh_num,
>>>>> reg_offset);
>>>>> return 0;
>>>>> }
>>>>> return -EINVAL;
>>>>
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>>> amd-gfx at lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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>
>
