Hi Joerg, Thanks for looking into this. We confirm that this workaround avoids the iommu log spam and that amdgpu appears to be working fine with it. Daniel On Wed, Mar 22, 2017 at 5:22 AM, joro at 8bytes.org <joro at 8bytes.org> wrote: > On Tue, Mar 21, 2017 at 04:30:55PM +0000, Deucher, Alexander wrote: >> > I am preparing a debug-patch that disables ATS for these GPUs so someone >> > with such a chip can test it. >> >> Thanks Joerg. > > Here is a debug patch, using the hard hammer of disabling the use of ATS > completly in the AMD IOMMU driver. If it fixes the issue I am going to > write a more upstreamable version. > > But for now, please test if this fixes the issue. > > Thanks, > > Joerg > > diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c > index 98940d1..f019aa6 100644 > --- a/drivers/iommu/amd_iommu.c > +++ b/drivers/iommu/amd_iommu.c > @@ -467,7 +467,7 @@ static int iommu_init_device(struct device *dev) > struct amd_iommu *iommu; > > iommu = amd_iommu_rlookup_table[dev_data->devid]; > - dev_data->iommu_v2 = iommu->is_iommu_v2; > + dev_data->iommu_v2 = false; > } > > dev->archdata.iommu = dev_data; > diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c > index 6130278..41d0e64 100644 > --- a/drivers/iommu/amd_iommu_init.c > +++ b/drivers/iommu/amd_iommu_init.c > @@ -171,7 +171,7 @@ int amd_iommus_present; > > /* IOMMUs have a non-present cache? */ > bool amd_iommu_np_cache __read_mostly; > -bool amd_iommu_iotlb_sup __read_mostly = true; > +bool amd_iommu_iotlb_sup __read_mostly = false; > > u32 amd_iommu_max_pasid __read_mostly = ~0; >
