On Fri, Mar 24, 2017 at 11:09 AM, Christian König
<deathsimple at vodafone.de> wrote:
> From: Christian König <christian.koenig at amd.com>
>
> Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the
> same info is available cached as enabled_rb_pipes_mask.
NACK. We need to implement the caching anyway for sr-iov. We can
just port the cache changes over from VI. Have you started looking at
that yet?
Alex
>
> Also remove duplicate mmCP_CPF_BUSY_STAT.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7e54d9dc..be0d47f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -296,11 +296,9 @@ static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
> { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
> { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
> { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
> - { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
> { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
> { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
> { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
> - { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true},
> { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true},
> { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false},
> };
> --
> 2.5.0
>
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