Makes sense, although the pattern elsewhere is to just start at 1 for
mec. Not sure if it's worth the effort to fix all of those cases up
too.
Series is:
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
On Tue, Jul 9, 2024 at 2:07 AM Sunil Khatri <sunil.khatri@xxxxxxx> wrote:
>
> GFX ME right now is one but this could change in
> future SOC's. Use no of ME for GFX as start point
> for ME for compute for GFX12.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 084b039eb765..f384be0d1800 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -4946,7 +4946,7 @@ static void gfx_v12_ip_dump(void *handle)
> for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
> for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
> /* ME0 is for GFX so start from 1 for CP */
> - soc24_grbm_select(adev, 1+i, j, k, 0);
> + soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
> for (reg = 0; reg < reg_count; reg++) {
> adev->gfx.ip_dump_compute_queues[index + reg] =
> RREG32(SOC15_REG_ENTRY_OFFSET(
> --
> 2.34.1
>
