On Thu, Jun 20, 2024 at 3:02 AM Min, Frank <Frank.Min@xxxxxxx> wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> From: Frank Min <Frank.Min@xxxxxxx>
>
> Access ltr through pci cfg space instead of mmio while programing aspm on gfx12
>
> Signed-off-by: Frank Min <Frank.Min@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
> index 5a20bb229788..39919e0892c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
> @@ -345,6 +345,7 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev) { #ifdef CONFIG_PCIEASPM
> uint32_t def, data;
> + u16 devctl2, ltr;
>
> def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);
> data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
> @@ -374,12 +375,17 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)
> if (def != data)
> WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
>
> - def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
> - data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
> + pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2);
> + data = def = devctl2;
> + data &= ~PCI_EXP_DEVCTL2_LTR_EN;
> if (def != data)
> - WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
> + pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, (u16)data);
> +
> + ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR);
>
> - WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
> + if (ltr) {
> + pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001);
> + }
>
> #if 0
> /* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */
> --
> 2.34.1
>
