When flushing gpu tlb using kiq for gfxhub, kiq ring is always
local by selecting kiq instance. Test shows mmreg write data packet's
higher bits then 16 have no effect when flush using kiq on gfxhub.
Also some variant have policy blocking higher offset when req/ack is set
with extra bits and can cause flush to timeout.
So keep the lower 16 bits only.
Remove redundant code.
Signed-off-by: Yiqing Yao <YiQing.Yao@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 350f6b6676f1..f3fe318e0c1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -853,8 +853,16 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
*/
if (adev->gfx.kiq[inst].ring.sched.ready &&
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
- uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
- uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
+
+ /*
+ * Select lower 16 bits to write in local xcc when flushing
+ * using kiq to write gfx as higher bits are always ignored
+ */
+ if (vmhub < AMDGPU_MMHUB0(0))
+ {
+ req = req & 0xffff;
+ ack = ack & 0xffff;
+ }
amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
1 << vmid, inst);
--
2.34.1
