On Thu, Jun 6, 2024 at 8:22 AM Harish Kasiviswanathan
<Harish.Kasiviswanathan@xxxxxxx> wrote:
>
> To achieve full occupancy CP hardware needs to know if CUs in SE are
> symmetrically or asymmetrically harvested
>
> v2: Reset is_symmetric_cus for each loop
>
> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index aecc2bcea145..d50dd6f4472a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -4203,9 +4203,10 @@ static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_i
> static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
> struct amdgpu_cu_info *cu_info)
> {
> - int i, j, k, counter, xcc_id, active_cu_number = 0;
> - u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
> + int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;
> + u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;
> unsigned disable_masks[4 * 4];
> + bool is_symmetric_cus;
>
> if (!adev || !cu_info)
> return -EINVAL;
> @@ -4223,6 +4224,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
>
> mutex_lock(&adev->grbm_idx_mutex);
> for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
> + is_symmetric_cus = true;
> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> mask = 1;
> @@ -4250,6 +4252,15 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
> ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
> cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
> }
> + if (i && is_symmetric_cus && prev_counter != counter)
> + is_symmetric_cus = false;
> + prev_counter = counter;
> + }
> + if (is_symmetric_cus) {
> + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);
> + tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);
> + tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);
> + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);
> }
> gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
> xcc_id);
> --
> 2.34.1
>
