From: Pratap Nirujogi <pratap.nirujogi@xxxxxxx> Remove temporary WA to disable ISP prefetch as MMHUB SAW is initialized to support ISP HW access GART memory using the TLSi path with prefetch enabled. Signed-off-by: Pratap Nirujogi <pratap.nirujogi@xxxxxxx> Reviewed-by: Mario Limonciello <mario.limonciello@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c | 12 ------------ drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h | 7 ------- drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c | 12 ------------ drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h | 7 ------- 4 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c index 962da37fb1f7..aac107898bae 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c @@ -104,18 +104,6 @@ static int isp_v4_1_0_hw_init(struct amdgpu_isp *isp) goto failure; } - /* - * Temporary WA added to disable MMHUB TLSi until the GART initialization - * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory - * using the TLSi path - */ - WREG32(mmDAGB0_WRCLI5_V4_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB0_WRCLI9_V4_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB0_WRCLI10_V4_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB0_WRCLI14_V4_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB0_WRCLI19_V4_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB0_WRCLI20_V4_1 >> 2, 0xFE5FEAA8); - return 0; failure: diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h index bd9e1f13c748..315f2822410c 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h @@ -32,13 +32,6 @@ #include "ivsrcid/isp/irqsrcs_isp_4_1.h" -#define mmDAGB0_WRCLI5_V4_1 0x6811C -#define mmDAGB0_WRCLI9_V4_1 0x6812C -#define mmDAGB0_WRCLI10_V4_1 0x68130 -#define mmDAGB0_WRCLI14_V4_1 0x68140 -#define mmDAGB0_WRCLI19_V4_1 0x68154 -#define mmDAGB0_WRCLI20_V4_1 0x68158 - #define MAX_ISP410_INT_SRC 8 void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp); diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c index 67f95f05ecca..4e17fa03f7b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c @@ -104,18 +104,6 @@ static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp) goto failure; } - /* - * Temporary WA added to disable MMHUB TLSi until the GART initialization - * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory - * using the TLSi path - */ - WREG32(mmDAGB1_WRCLI5_V4_1_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB1_WRCLI9_V4_1_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB1_WRCLI10_V4_1_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB1_WRCLI14_V4_1_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB1_WRCLI19_V4_1_1 >> 2, 0xFE5FEAA8); - WREG32(mmDAGB1_WRCLI20_V4_1_1 >> 2, 0xFE5FEAA8); - return 0; failure: diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h index 6bfb1de191a0..dfb9522c9d6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h @@ -32,13 +32,6 @@ #include "ivsrcid/isp/irqsrcs_isp_4_1.h" -#define mmDAGB1_WRCLI5_V4_1_1 0x68420 -#define mmDAGB1_WRCLI9_V4_1_1 0x68430 -#define mmDAGB1_WRCLI10_V4_1_1 0x68434 -#define mmDAGB1_WRCLI14_V4_1_1 0x68444 -#define mmDAGB1_WRCLI19_V4_1_1 0x68458 -#define mmDAGB1_WRCLI20_V4_1_1 0x6845C - #define MAX_ISP411_INT_SRC 8 void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp); -- 2.37.3
