On Fri, Apr 26, 2024 at 9:57 AM Shashank Sharma <shashank.sharma@xxxxxxx> wrote:
>
> Current MES GFX mask prevents FW to enable oversubscription. This patch
> does the following:
> - Fixes the mask values and adds a description for the same.
> - Removes the central mask setup and makes it IP specific, as it would
> be different when the number of pipes and queues are different.
>
> V9: introduce this patch in the series
>
> Cc: Christian König <Christian.Koenig@xxxxxxx>
> Cc: Alex Deucher <alexander.deucher@xxxxxxx>
> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxx>
> Signed-off-by: Arvind Yadav <arvind.yadav@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 -
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 9 +++++++--
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 9 +++++++--
> 4 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index a00cf4756ad0..b405fafc0b71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -151,9 +151,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> adev->mes.compute_hqd_mask[i] = 0xc;
> }
>
> - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
> - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
> -
> for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
> if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) <
> IP_VERSION(6, 0, 0))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index 4c8fc3117ef8..598556619337 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -110,7 +110,6 @@ struct amdgpu_mes {
> uint32_t vmid_mask_gfxhub;
> uint32_t vmid_mask_mmhub;
> uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
> - uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
> uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
> uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
> uint32_t sch_ctx_offs;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 1e5ad1e08d2a..4d1121d1a1e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -290,8 +290,13 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)
> mes_set_hw_res_pkt.compute_hqd_mask[i] =
> mes->compute_hqd_mask[i];
>
> - for (i = 0; i < MAX_GFX_PIPES; i++)
> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
> + /*
> + * GFX pipe 0 queue 0 is being used by kernel
> + * Set GFX pipe 0 queue 1 for MES scheduling
> + * GFX pipe 1 can't be used for MES due to HW limitation.
> + */
> + mes_set_hw_res_pkt.gfx_hqd_mask[0] = 0x2;
> + mes_set_hw_res_pkt.gfx_hqd_mask[1] = 0;
>
> for (i = 0; i < MAX_SDMA_PIPES; i++)
> mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 63f281a9984d..feb7fa2c304c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -387,8 +387,13 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
> mes_set_hw_res_pkt.compute_hqd_mask[i] =
> mes->compute_hqd_mask[i];
>
> - for (i = 0; i < MAX_GFX_PIPES; i++)
> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
> + /*
> + * GFX pipe 0 queue 0 is being used by kernel
> + * Set GFX pipe 0 queue 1 for MES scheduling
> + * GFX pipe 1 can't be used for MES due to HW limitation.
> + */
> + mes_set_hw_res_pkt.gfx_hqd_mask[0] = 0x2;
> + mes_set_hw_res_pkt.gfx_hqd_mask[1] = 0;
FWIW, I think this should work on pipe1. Might be worth playing with.
The attached patches should enable pipe1 for kernel queues similar to
gfx10. Anyway, something for the future.
Patch is:
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
Alex
>
> for (i = 0; i < MAX_SDMA_PIPES; i++)
> mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
> --
> 2.43.2
>
From 793806a205b48d1328635051eac49f9357885bce Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Thu, 11 Apr 2024 17:16:09 -0400
Subject: [PATCH 2/2] drm/amdgpu/gfx11: add pipe1 hardware support
Enable gfx pipe1 hardware support.
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 81a35d0f0a58e..357829036662e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -51,6 +51,7 @@
#include "mes_v11_0.h"
#define GFX11_NUM_GFX_RINGS 1
+#define GFX11_NUM_GFX_RINGS_2 2
#define GFX11_MEC_HPD_SIZE 2048
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -1342,7 +1343,7 @@ static int gfx_v11_0_sw_init(void *handle)
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
adev->gfx.me.num_me = 1;
- adev->gfx.me.num_pipe_per_me = 1;
+ adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 2;
adev->gfx.mec.num_pipe_per_mec = 4;
@@ -4714,7 +4715,16 @@ static int gfx_v11_0_early_init(void *handle)
adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
- adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
+ switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 3):
+ adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS_2;
+ break;
+ default:
+ adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
+ break;
+ }
adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
AMDGPU_MAX_COMPUTE_RINGS);
--
2.44.0
From 19f0408347bf1b7b7d15280e1bf7230054fc61d5 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Thu, 11 Apr 2024 17:13:13 -0400
Subject: [PATCH 1/2] drm/amdgpu/gfx11: select HDP ref/mask according to gfx
ring pipe
Use correct ref/mask for differnent gfx ring pipe. Ported from
ZhenGuo's patch for gfx10.
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ad6431013c738..81a35d0f0a58e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5293,7 +5293,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
}
reg_mem_engine = 0;
} else {
- ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
+ ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
reg_mem_engine = 1; /* pfp */
}
--
2.44.0
