[Public]
This patch is,
Reviewed-by: Tim Huang <Tim.Huang@xxxxxxx>
Best Regards,
Tim Huang
> -----Original Message-----
> From: Jesse Zhang <jesse.zhang@xxxxxxx>
> Sent: Sunday, April 28, 2024 5:38 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian
> <Christian.Koenig@xxxxxxx>; Huang, Tim <Tim.Huang@xxxxxxx>; Zhang,
> Jesse(Jie) <Jesse.Zhang@xxxxxxx>; Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>
> Subject: [PATCH 1/3 V2] drm/amd/pm: Fix negative array index read warning for
> pptable->DpmDescriptor
>
> Avoid using the negative values
> for clk_idex as an index into an array pptable->DpmDescriptor.
>
> V2: fix clk_index return check (Tim Huang)
>
> Signed-off-by: Jesse Zhang <Jesse.Zhang@xxxxxxx>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 27 ++++++++++++++-----
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 5a68d365967f..c06e0d6e3017 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -1219,19 +1219,22 @@ static int
> navi10_get_current_clk_freq_by_table(struct smu_context *smu,
> value);
> }
>
> -static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> enum smu_clk_type clk_type)
> +static int navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> +enum smu_clk_type clk_type)
> {
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> DpmDescriptor_t *dpm_desc = NULL;
> - uint32_t clk_index = 0;
> + int clk_index = 0;
>
> clk_index = smu_cmn_to_asic_specific_index(smu,
> CMN2ASIC_MAPPING_CLK,
> clk_type);
> + if (clk_index < 0)
> + return clk_index;
> +
> dpm_desc = &pptable->DpmDescriptor[clk_index];
>
> /* 0 - Fine grained DPM, 1 - Discrete DPM */
> - return dpm_desc->SnapToDiscrete == 0;
> + return dpm_desc->SnapToDiscrete == 0 ? 1 : 0;
> }
>
> static inline bool navi10_od_feature_is_supported(struct
> smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
> @@ -1287,7 +1290,11 @@ static int navi10_emit_clk_levels(struct smu_context
> *smu,
> if (ret)
> return ret;
>
> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret) {
> for (i = 0; i < count; i++) {
> ret = smu_v11_0_get_dpm_freq_by_index(smu,
> clk_type, i,
> &value);
> @@ -1496,7 +1503,11 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
> if (ret)
> return size;
>
> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret) {
> for (i = 0; i < count; i++) {
> ret = smu_v11_0_get_dpm_freq_by_index(smu,
> clk_type, i, &value);
> if (ret)
> @@ -1665,7 +1676,11 @@ static int navi10_force_clk_levels(struct smu_context
> *smu,
> case SMU_UCLK:
> case SMU_FCLK:
> /* There is only 2 levels for fine grained DPM */
> - if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (ret) {
> soft_max_level = (soft_max_level >= 1 ? 1 : 0);
> soft_min_level = (soft_min_level >= 1 ? 1 : 0);
> }
> --
> 2.25.1
