Re: [PATCH v2 2/2] drm/amdgpu/pm: Fix uninitialized variable warning

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Series is:
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>

From: Ma, Jun <Jun.Ma2@xxxxxxx>
Sent: Monday, April 29, 2024 3:58 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Cc: Feng, Kenneth <Kenneth.Feng@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Wang, Yang(Kevin) <KevinYang.Wang@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Ma, Jun <Jun.Ma2@xxxxxxx>
Subject: [PATCH v2 2/2] drm/amdgpu/pm: Fix uninitialized variable warning
 
Check return value of smum_send_msg_to_smc to fix
uninitialized variable varning

Signed-off-by: Ma Jun <Jun.Ma2@xxxxxxx>
---
 .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  | 21 +++++++++++++----
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 20 ++++++++++++----
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 23 ++++++++++++++-----
 3 files changed, 48 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 38d5605117ff..a8c732e07006 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1558,7 +1558,10 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
                 }
 
                 if (input[0] == 0) {
-                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
+                       ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
+                       if (ret)
+                               return ret;
+
                         if (input[1] < min_freq) {
                                 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
                                         input[1], min_freq);
@@ -1566,7 +1569,10 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
                         }
                         smu10_data->gfx_actual_soft_min_freq = input[1];
                 } else if (input[0] == 1) {
-                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
+                       ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
+                       if (ret)
+                               return ret;
+
                         if (input[1] > max_freq) {
                                 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
                                         input[1], max_freq);
@@ -1581,10 +1587,15 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
                         pr_err("Input parameter number not correct\n");
                         return -EINVAL;
                 }
-               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
-               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
-
+               ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
+               if (ret)
+                       return ret;
                 smu10_data->gfx_actual_soft_min_freq = min_freq;
+
+               ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
+               if (ret)
+                       return ret;
+
                 smu10_data->gfx_actual_soft_max_freq = max_freq;
         } else if (type == PP_OD_COMMIT_DPM_TABLE) {
                 if (size != 0) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
index c223e3a6bfca..10fd4e9f016c 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
@@ -293,12 +293,12 @@ static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
-static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
+static int vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 {
         struct vega12_hwmgr *data = "" vega12_hwmgr *)(hwmgr->backend);
         struct amdgpu_device *adev = hwmgr->adev;
         uint32_t top32, bottom32;
-       int i;
+       int i, ret;
 
         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
                         FEATURE_DPM_PREFETCHER_BIT;
@@ -364,10 +364,16 @@ static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
         }
 
         /* Get the SN to turn into a Unique ID */
-       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
-       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
+       ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
+       if (ret)
+               return ret;
+       ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
+       if (ret)
+               return ret;
 
         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
+
+       return 0;
 }
 
 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
@@ -410,7 +416,11 @@ static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
         vega12_set_features_platform_caps(hwmgr);
 
-       vega12_init_dpm_defaults(hwmgr);
+       result = vega12_init_dpm_defaults(hwmgr);
+       if (result) {
+               pr_err("%s failed\n", __func__);
+               return result;
+       }
 
         /* Parse pptable data read from VBIOS */
         vega12_set_private_data_based_on_pptable(hwmgr);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index f9efb0bad807..bf1b829f9d68 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -328,12 +328,12 @@ static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
-static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
+static int vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 {
         struct vega20_hwmgr *data = "" vega20_hwmgr *)(hwmgr->backend);
         struct amdgpu_device *adev = hwmgr->adev;
         uint32_t top32, bottom32;
-       int i;
+       int i, ret;
 
         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
                         FEATURE_DPM_PREFETCHER_BIT;
@@ -404,10 +404,17 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
         }
 
         /* Get the SN to turn into a Unique ID */
-       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
-       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
+       ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
+       if (ret)
+               return ret;
+
+       ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
+       if (ret)
+               return ret;
 
         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
+
+       return 0;
 }
 
 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
@@ -427,6 +434,7 @@ static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 {
         struct vega20_hwmgr *data;
         struct amdgpu_device *adev = hwmgr->adev;
+       int result;
 
         data = "" vega20_hwmgr), GFP_KERNEL);
         if (data == NULL)
@@ -452,8 +460,11 @@ static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
         vega20_set_features_platform_caps(hwmgr);
 
-       vega20_init_dpm_defaults(hwmgr);
-
+       result = vega20_init_dpm_defaults(hwmgr);
+       if (result) {
+               pr_err("%s failed\n", __func__);
+               return result;
+       }
         /* Parse pptable data read from VBIOS */
         vega20_set_private_data_based_on_pptable(hwmgr);
 
--
2.34.1


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