On Sun, Apr 28, 2024 at 7:12 AM Ma Jun <Jun.Ma2@xxxxxxx> wrote:
>
> Check return value of smum_send_msg_to_smc to fix
> uninitialized variable varning
>
> Signed-off-by: Ma Jun <Jun.Ma2@xxxxxxx>
> ---
> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 ++++++++++++++-----
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 8 +++++--
> .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 6 ++++--
> .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 6 ++++--
> 4 files changed, 30 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 0b181bc8931c..f62381b189ad 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1554,7 +1554,10 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
> }
>
> if (input[0] == 0) {
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
> + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
> + if (ret)
> + return ret;
> +
> if (input[1] < min_freq) {
> pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
> input[1], min_freq);
> @@ -1562,7 +1565,10 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
> }
> smu10_data->gfx_actual_soft_min_freq = input[1];
> } else if (input[0] == 1) {
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
> + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
> + if (ret)
> + return ret;
> +
> if (input[1] > max_freq) {
> pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
> input[1], max_freq);
> @@ -1577,10 +1583,15 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
> pr_err("Input parameter number not correct\n");
> return -EINVAL;
> }
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
> -
> + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
> + if (ret)
> + return ret;
> smu10_data->gfx_actual_soft_min_freq = min_freq;
> +
> + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
> + if (ret)
> + return ret;
> +
> smu10_data->gfx_actual_soft_max_freq = max_freq;
> } else if (type == PP_OD_COMMIT_DPM_TABLE) {
> if (size != 0) {
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 74a33b9ace6c..c60666f64601 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2486,9 +2486,13 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
> struct vega10_hwmgr *data = hwmgr->backend;
> AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
>
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
> + result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
> + if (result)
> + return result;
>
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
> + result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
> + if (result)
> + return result;
>
> serial_number = ((uint64_t)bottom32 << 32) | top32;
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> index c223e3a6bfca..9dd407134770 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> @@ -364,8 +364,10 @@ static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
> }
>
> /* Get the SN to turn into a Unique ID */
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
> + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32))
> + return;
> + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32))
> + return;
>
> adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
> }
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> index f9efb0bad807..3a95f7c4c6e3 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> @@ -404,8 +404,10 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
> }
>
> /* Get the SN to turn into a Unique ID */
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
> + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32))
> + return;
> + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32))
> + return;
>
> adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
> }
Please align with Tim on the powerplay changes. E.g., See this patch:
drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr
I'd like to have consistent function signatures for these functions.
Alex
> --
> 2.34.1
>
