On Wed, Apr 17, 2024 at 9:02 AM Li Ma <li.ma@xxxxxxx> wrote:
>
> smu v14.0.1 re-used smu v14.0.0
>
> Signed-off-by: Li Ma <li.ma@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> index 3bc9662fbd28..3ad3d20830fc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> @@ -136,7 +136,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
> 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
> mp1_fw_flags = RREG32_PCIE(MP1_Public |
> (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
> else
> @@ -209,7 +209,7 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
> struct amdgpu_device *adev = smu->adev;
> uint32_t mp1_fw_flags;
>
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
> mp1_fw_flags = RREG32_PCIE(MP1_Public |
> (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
> else
> @@ -856,7 +856,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
> // TODO
>
> /* For MP1 SW irqs */
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
> val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
> val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
> WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
> @@ -872,7 +872,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
> // TODO
>
> /* For MP1 SW irqs */
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
> val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
> val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
> val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
> --
> 2.25.1
>
