Re: [PATCH] drm/amdgpu: set vm_update_mode=0 as default for NV32 in SRIOV case

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Am 28.03.24 um 00:34 schrieb Danijel Slivka:
For asic with VF MMIO access protection avoid using CPU for VM table updates.
CPU pagetable updates have issues with HDP flush as VF MMIO access protection
blocks write to BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL register
during sriov runtime.

Well big NAK to the reasoning. HDP flush is *mandatory* to work correctly.

This not only includes flushes for CPU based VM updates, but also GART updates.

Without reliable HDP flushes the driver is simply not stable.


Signed-off-by: Danijel Slivka <danijel.slivka@xxxxxxx>
  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index aed60aaf1a55..a3012c9aa92b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -724,7 +724,8 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
  			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
- if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
+	if ((amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) ||
+		adev->pdev->device == 0x7461)
  		/* VF MMIO access (except mailbox range) from CPU
  		 * will be blocked during sriov runtime

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