Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> From: Junwei Zhang <Jerry.Zhang at amd.com>
>
> Signed-off-by: Flora Cui <Flora.Cui at amd.com>
> Reviewed-by: Jammy Zhou <Jammy.Zhou at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 ++++++
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 24 +++++++++++++++++++++---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17 +++++++++++++----
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 7 +++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 7 +++++++
> 5 files changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 57eaf71..b2ff9e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -165,6 +165,12 @@ struct amdgpu_vm_manager {
> /* partial resident texture handling */
> spinlock_t prt_lock;
> atomic_t num_prt_users;
> +
> + /* vm aperture */
> + u64 shared_aperture_start;
> + u64 shared_aperture_end;
> + u64 private_aperture_start;
> + u64 private_aperture_end;
Apertures doesn't belong in the VM structure, but rather in amdgpu_mc.
Christian.
> };
>
> void amdgpu_vm_manager_init(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index e471c08..cd6a6ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1889,7 +1889,8 @@ static void gfx_v7_0_config_init(struct amdgpu_device *adev)
> */
> static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
> {
> - u32 tmp, sh_mem_cfg;
> + u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
> + u32 tmp;
> int i;
>
> WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
> @@ -1920,15 +1921,32 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
> /* where to put LDS, scratch, GPUVM in FSA64 space */
> sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
> SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> + sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
> + MTYPE_NC);
> + sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
> + MTYPE_UC);
> + sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
> +
> + sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
> + SWIZZLE_ENABLE, 1);
> + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> + ELEMENT_SIZE, 1);
> + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> + INDEX_STRIDE, 3);
>
> mutex_lock(&adev->srbm_mutex);
> - for (i = 0; i < 16; i++) {
> + for (i = 0; i < adev->vm_manager.num_ids; i++) {
> + if (i == 0)
> + sh_mem_base = 0;
> + else
> + sh_mem_base = adev->vm_manager.shared_aperture_start >> 48;
> cik_srbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
> WREG32(mmSH_MEM_APE1_BASE, 1);
> WREG32(mmSH_MEM_APE1_LIMIT, 0);
> - WREG32(mmSH_MEM_BASES, 0);
> + WREG32(mmSH_MEM_BASES, sh_mem_base);
> + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
> }
> cik_srbm_select(adev, 0, 0, 0, 0);
> mutex_unlock(&adev->srbm_mutex);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 5dcf8db..af6294f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3859,7 +3859,7 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
>
> static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
> {
> - u32 tmp;
> + u32 tmp, sh_static_mem_cfg;
> int i;
>
> WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
> @@ -3874,8 +3874,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
>
> /* XXX SH_MEM regs */
> /* where to put LDS, scratch, GPUVM in FSA64 space */
> + sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
> + SWIZZLE_ENABLE, 1);
> + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> + ELEMENT_SIZE, 1);
> + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> + INDEX_STRIDE, 3);
> mutex_lock(&adev->srbm_mutex);
> - for (i = 0; i < 16; i++) {
> + for (i = 0; i < adev->vm_manager.num_ids; i++) {
> vi_srbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> if (i == 0) {
> @@ -3884,17 +3890,20 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
> tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
> SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> WREG32(mmSH_MEM_CONFIG, tmp);
> + WREG32(mmSH_MEM_BASES, 0);
> } else {
> tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
> - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
> + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
> tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
> SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> WREG32(mmSH_MEM_CONFIG, tmp);
> + tmp = adev->vm_manager.shared_aperture_start >> 48;
> + WREG32(mmSH_MEM_BASES, tmp);
> }
>
> WREG32(mmSH_MEM_APE1_BASE, 1);
> WREG32(mmSH_MEM_APE1_LIMIT, 0);
> - WREG32(mmSH_MEM_BASES, 0);
> + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
> }
> vi_srbm_select(adev, 0, 0, 0, 0);
> mutex_unlock(&adev->srbm_mutex);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 552bf6b..dc2b4c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -726,6 +726,13 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
> * amdkfd will use VMIDs 8-15
> */
> adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
> + adev->vm_manager.shared_aperture_end =
> + adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
> + adev->vm_manager.private_aperture_start =
> + adev->vm_manager.shared_aperture_end + 1;
> + adev->vm_manager.private_aperture_end =
> + adev->vm_manager.private_aperture_start + (4ULL << 30) - 1;
> amdgpu_vm_manager_init(adev);
>
> /* base offset of vram pages */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index f2bd016..81b1a49 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -857,6 +857,13 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
> * amdkfd will use VMIDs 8-15
> */
> adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
> + adev->vm_manager.shared_aperture_end =
> + adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
> + adev->vm_manager.private_aperture_start =
> + adev->vm_manager.shared_aperture_end + 1;
> + adev->vm_manager.private_aperture_end =
> + adev->vm_manager.private_aperture_start + (4ULL << 30) - 1;
> amdgpu_vm_manager_init(adev);
>
> /* base offset of vram pages */
