[Public]
> -----Original Message-----
> From: Liang, Prike <Prike.Liang@xxxxxxx>
> Sent: Thursday, February 1, 2024 3:58 AM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Sharma, Deepak
> <Deepak.Sharma@xxxxxxx>; Liang, Prike <Prike.Liang@xxxxxxx>
> Subject: [PATCH 2/2] drm/amdgpu: reset gpu for s3 suspend abort case
>
> In the s3 suspend abort case some type of gfx9 power rail not turn off from
> FCH side and this will put the GPU in an unknown power status, so let's reset
> the gpu to a known good power state before reinitialize gpu device.
>
> Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 15033efec2ba..c64c01e2944a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1298,10 +1298,32 @@ static int soc15_common_suspend(void
> *handle)
> return soc15_common_hw_fini(adev);
> }
>
> +static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) {
> + u32 sol_reg;
> +
> + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> +
> + /* Will reset for the following suspend abort cases.
> + * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> + * 2) S3 suspend abort and TOS already launched.
> + */
> + if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> + !adev->suspend_complete &&
> + sol_reg)
> + return true;
> +
> + return false;
> +}
> +
> static int soc15_common_resume(void *handle) {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + if (soc15_need_reset_on_resume(adev)) {
> + dev_info(adev->dev, "S3 suspend abort case, let's reset
> ASIC.\n");
> + soc15_asic_reset(adev);
> + }
> return soc15_common_hw_init(adev);
> }
>
> --
> 2.34.1
