when MCBP supported, we will set pre_enb bit for those
IBs with PREEMPT flag tagged
Change-Id: I753a850e6acdce56e22f873bc7fee8874c5a1a12
Signed-off-by: Monk Liu <Monk.Liu at amd.com>
---
include/uapi/drm/amdgpu_drm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 1966fee..18ee1a4 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -429,6 +429,9 @@ union drm_amdgpu_cs {
/* Preamble flag, which means the IB could be dropped if no context switch */
#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
+/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
+#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
--
2.7.4
