[Public]
>-----Original Message-----
>From: Zhang, Yifan <Yifan1.Zhang@xxxxxxx>
>Sent: Monday, January 29, 2024 5:06 PM
>To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian
><Christian.Koenig@xxxxxxx>; Huang, Tim <Tim.Huang@xxxxxxx>; Yu, Lang
><Lang.Yu@xxxxxxx>; Zhang, Yifan <Yifan1.Zhang@xxxxxxx>
>Subject: [PATCH] drm/amdgpu: remove golden setting for gfx 11.5.0
>
>No need to set golden settings in driver from gfx 11.5.0 onwards
>
>Signed-off-by: Yifan Zhang <yifan1.zhang@xxxxxxx>
>---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 32 ++------------------------
> 1 file changed, 2 insertions(+), 30 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>index c1e000010760..4e99af904e04 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>@@ -90,10 +90,6 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
> MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
> MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
>
>-static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000,
>0x20000000)
>-};
>-
> static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL,
>0x9fff8fff, 0x00000010), @@ -104,24 +100,8 @@ static const struct
>soc15_reg_golden golden_settings_gc_11_0_1[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd,
>0x00000008),
> SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1,
>0xfff891ff, 0x55480100),
> SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff,
>0x01030000),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff,
>0x0000000a)
>-};
>-
>-static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff,
>0x00000800),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff,
>0x00000242),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff,
>0x00000500),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK,
>0xffffffff, 0xfffffff3),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK,
>0xffffffff, 0xfffffff3),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb,
>0x00f40188),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff,
>0x80009007),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff,
>0x00880007),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff,
>0x00010000),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff,
>0x01030000),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000,
>0x00000000),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff,
>0x0000200a),
>- SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff,
>0x0000048f)
>+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff,
>0x0000000a),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000,
>0x20000000)
> };
>
> #define DEFAULT_SH_MEM_CONFIG \
>@@ -304,17 +284,9 @@ static void gfx_v11_0_init_golden_registers(struct
>amdgpu_device *adev)
> golden_settings_gc_11_0_1,
> (const
>u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
> break;
>- case IP_VERSION(11, 5, 0):
>- soc15_program_register_sequence(adev,
>- golden_settings_gc_11_5_0,
>- (const
>u32)ARRAY_SIZE(golden_settings_gc_11_5_0));
>- break;
> default:
> break;
> }
>- soc15_program_register_sequence(adev,
>- golden_settings_gc_11_0,
>- (const
>u32)ARRAY_SIZE(golden_settings_gc_11_0));
>
Remove golden_settings_gc_11_0 may affect all gfx11 ASICs.
Regards,
Lang
> }
>
>--
>2.37.3
