Re: [PATCH v2 1/2] drm/amdgpu: Reset IH OVERFLOW_CLEAR bit

[Christian König <christian.koenig@xxxxxxx>]

Am 18.01.24 um 19:54 schrieb Friedrich Vock:
> Allows us to detect subsequent IH ring buffer overflows as well.
>
> Cc: Joshua Ashton <joshua@xxxxxxxxx>
> Cc: Alex Deucher <alexander.deucher@xxxxxxx>
> Cc: Christian König <christian.koenig@xxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
>
> Signed-off-by: Friedrich Vock <friedrich.vock@xxxxxx>
> ---
> v2: Reset CLEAR_OVERFLOW bit immediately after setting it
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h  | 2 ++
>   drivers/gpu/drm/amd/amdgpu/cik_ih.c     | 7 +++++++
>   drivers/gpu/drm/amd/amdgpu/cz_ih.c      | 6 ++++++
>   drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 6 ++++++
>   drivers/gpu/drm/amd/amdgpu/ih_v6_0.c    | 7 +++++++
>   drivers/gpu/drm/amd/amdgpu/ih_v6_1.c    | 8 ++++++++
>   drivers/gpu/drm/amd/amdgpu/navi10_ih.c  | 7 +++++++
>   drivers/gpu/drm/amd/amdgpu/si_ih.c      | 7 +++++++
>   drivers/gpu/drm/amd/amdgpu/tonga_ih.c   | 7 +++++++
>   drivers/gpu/drm/amd/amdgpu/vega10_ih.c  | 7 +++++++
>   drivers/gpu/drm/amd/amdgpu/vega20_ih.c  | 7 +++++++
>   11 files changed, 71 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index 508f02eb0cf8..6041ec727f06 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -69,6 +69,8 @@ struct amdgpu_ih_ring {
>   	unsigned		rptr;
>   	struct amdgpu_ih_regs	ih_regs;
>
> +	bool overflow;
> +

That flag isn't needed any more in this patch as far as I can see.

Regards,
Christian.

>   	/* For waiting on IH processing at checkpoint. */
>   	wait_queue_head_t wait_process;
>   	uint64_t		processed_timestamp;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 6f7c031dd197..bbadf2e530b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -204,6 +204,13 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
>   		tmp = RREG32(mmIH_RB_CNTL);
>   		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
>   		WREG32(mmIH_RB_CNTL, tmp);
> +
> +		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +		 * can be detected.
> +		 */
> +		tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> +		WREG32(mmIH_RB_CNTL, tmp);
> +		ih->overflow = true;
>   	}
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index b8c47e0cf37a..e5c4ed44bad9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -216,6 +216,12 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32(mmIH_RB_CNTL, tmp);
>
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32(mmIH_RB_CNTL, tmp);
> +	ih->overflow = true;
>
>   out:
>   	return (wptr & ih->ptr_mask);
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index aecad530b10a..075e5c1a5549 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -215,6 +215,12 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32(mmIH_RB_CNTL, tmp);
>
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32(mmIH_RB_CNTL, tmp);
> +	ih->overflow = true;
>
>   out:
>   	return (wptr & ih->ptr_mask);
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index d9ed7332d805..d0a5a08edd55 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -418,6 +418,13 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
>   	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +	ih->overflow = true;
>   out:
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index 8fb05eae340a..6bf4f210ef74 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -418,6 +418,14 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
>   	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +	ih->overflow = true;
> +
>   out:
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index e64b33115848..cdbe7d01490e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -442,6 +442,13 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
>   	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +	ih->overflow = true;
>   out:
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 9a24f17a5750..398fbc296cac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -119,6 +119,13 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,
>   		tmp = RREG32(IH_RB_CNTL);
>   		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
>   		WREG32(IH_RB_CNTL, tmp);
> +
> +		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +		 * can be detected.
> +		 */
> +		tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> +		WREG32(IH_RB_CNTL, tmp);
> +		ih->overflow = true;
>   	}
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 917707bba7f3..1d1e064be7d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -219,6 +219,13 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32(mmIH_RB_CNTL, tmp);
>
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32(mmIH_RB_CNTL, tmp);
> +	ih->overflow = true;
> +
>   out:
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index d364c6dd152c..619087a4c4ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -373,6 +373,13 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
>
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +	ih->overflow = true;
> +
>   out:
>   	return (wptr & ih->ptr_mask);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> index ddfc6941f9d5..f42f8e5dbe23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> @@ -421,6 +421,13 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
>   	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
>   	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
>
> +	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> +	 * can be detected.
> +	 */
> +	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> +	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> +	ih->overflow = true;
> +
>   out:
>   	return (wptr & ih->ptr_mask);
>   }
> --
> 2.43.0