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[AMD Official Use Only - General]
Yes, those regs are restricted to PF writes. I should update the commit message
From: Dhume, Samir <Samir.Dhume@xxxxxxx>
Sent: Wednesday, November 8, 2023 9:54 AM
To: Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Subject: RE: [PATCH] drm/amdgpu: Do not program HDP_MISC_CNTL in hdp_v4_0.c under SRIOV
[AMD Official Use Only - General]
Do you also need to skip programming of mmHDP_NONSURFACE_BASE and mmHDP_NONSURFACE_BASE_HI?
-----Original Message-----
From: Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu@xxxxxxx>
Sent: Tuesday, November 7, 2023 2:32 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Dhume, Samir <Samir.Dhume@xxxxxxx>; Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu@xxxxxxx>
Subject: [PATCH] drm/amdgpu: Do not program HDP_MISC_CNTL in hdp_v4_0.c under SRIOV
This register is blocked for VF access.
Signed-off-by: Victor Lu <victorchengchi.lu@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 3f3a6445c006..bf3bdf67abb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -145,6 +145,11 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
break;
}
+ /* Do not program registers if VF */
+ if (amdgpu_sriov_vf(adev)) {
+ return;
+ }
+
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
--
2.34.1
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